Clock node capacity minimization using lookup table based controller for ultrasound and medical imaging processor

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Abstract

Low power system on-chip design without performance degradation is the most critical design issue for the processor involved in medical image diagnosis. To make the medical device portable, it is necessary to reduce the processor size with less power consumption. The performance of the chip is affected drastically due to rise in temperature produced by unnecessary internal switching. Hence it is necessary for power optimization and minimizing unnecessary switching. In our proposed work, an efficient level shifting scheme of clock signal can be achieved by utilizing lookup table based level conversion scheme in clock node. The switching activity is verified for various logic network using multi-level conversion scheme with Conditional Capture technique and Improved Conditional Capture technique. It ensures the power saving by turning on a functional logic block only when required and minimizes the unnecessary clock node activity. This paper analyzes the proposed work in 0.6 \(\upmu \)m, 50 n CMOS processor and compares the results with the existing power and delay optimization techniques as it is widely applicable for image analysis.

Keywords

Clock gating Conditional capture Lookup table Clustered voltage scaling (CVS) Sequential circuits 

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringSri Ramakrishna Institute of TechnologyCoimbatoreIndia
  2. 2.Department of ECECoimbatore Institute of Engineering and TechnologyCoimbatoreIndia

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