Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced by the use of a high resolution digital-to-time converter with its range and duty cycle calibration in background. Also, the nonlinearity of the analog front-end circuit in the proposed hearing aid SoC is reduced by introducing a switching block based dynamic element matching process. Furthermore, an improved noise reduction algorithm is proposed based on pitch based voice activity detector and multiband complex spectral subtraction to improve the performance of the proposed hearing Aid SoC. The proposed hearing aid SoC is designed in an 180 nm CMOS technology. The simulation results show that, integrated jitter of the proposed structure is reduced to 0.9 psrms and it achieves a signal to noise ratio of 89.24 dB. The total power consumption of this hearing aid is only 996 μW for 1.2 V supply that shows the superiority of the proposed work than existing works.
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Meenakshi Vidya, P., Sudha, S. Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction. Analog Integr Circ Sig Process (2020). https://doi.org/10.1007/s10470-020-01670-5
- Hearing aid SoC
- Analog front-end (AFE)
- Fractional dividers (FDIV)
- DSP platform
- Noise reduction (NR)