Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction


Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced by the use of a high resolution digital-to-time converter with its range and duty cycle calibration in background. Also, the nonlinearity of the analog front-end circuit in the proposed hearing aid SoC is reduced by introducing a switching block based dynamic element matching process. Furthermore, an improved noise reduction algorithm is proposed based on pitch based voice activity detector and multiband complex spectral subtraction to improve the performance of the proposed hearing Aid SoC. The proposed hearing aid SoC is designed in an 180 nm CMOS technology. The simulation results show that, integrated jitter of the proposed structure is reduced to 0.9 psrms and it achieves a signal to noise ratio of 89.24 dB. The total power consumption of this hearing aid is only 996 μW for 1.2 V supply that shows the superiority of the proposed work than existing works.

This is a preview of subscription content, log in to check access.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12


  1. 1.

    Mohanty, B. K., Panda, G., & Puhan, N. B. (2018). Hardware design for VLSI implementation of acoustic feedback canceller in hearing aids. Circuits, Systems, and Signal Processing,37(4), 1383–1406.

    MathSciNet  Article  Google Scholar 

  2. 2.

    Chen, C., Chen, L., Fan, J., Yu, Z., Yang, J., Hu, X., et al. (2016). A 1 V, 1.1 mW mixed-signal hearing aid SoC in 0.13 μm CMOS process. In 2016 IEEE international symposium on circuits and systems (ISCAS) (pp. 225–228).

  3. 3.

    Chen, C., Fan, J., Hu, X., & Hei, Y. (2015). A low power, high performance analog front-end circuit for 1 V digital hearing aid SoC. Circuits, Systems, and Signal Processing,34(5), 1391–1404.

    Article  Google Scholar 

  4. 4.

    Seifert, C., Payá-Vayá, G., Blume, H., Herzke, T., & Hohmann, V. (2015). A mobile SoC-based platform for evaluating hearing aid algorithms and architectures. In 2015 IEEE 5th international conference on consumer electronics-Berlin (ICCE-Berlin) (pp. 93–97).

  5. 5.

    Karlsson, A. (2016). Design of energy-efficient high-performance ASIP-DSP platforms. PhD dissertation, Linköping University Electronic Press.

  6. 6.

    Hodgson, S.-A., Herdering, R., Shekhawat, G. S., & Searchfield, G. D. (2017). A crossover trial comparing wide dynamic range compression and frequency compression in hearing aids for tinnitus therapy. Disability and Rehabilitation: Assistive Technology,12(1), 97–103.

    Google Scholar 

  7. 7.

    Wu, Y.-H., Stangl, E., Chipara, O., ShabihHasan, S., DeVries, S., & Oleson, J. (2019). Efficacy and effectiveness of advanced hearing aid directional and noise reduction technologies for older adults with mild to moderate hearing loss. Ear and Hearing,40(4), 805–822.

    Article  Google Scholar 

  8. 8.

    Mishra, P., Ganguly, A., Küçük, A. & Panahi, I. M. S. (2017). Unsupervised noise-aware adaptive feedback cancellation for hearing aid devices under noisy speech framework. In 2017 IEEE signal processing in medicine and biology symposium (SPMB) (pp. 1–5).

  9. 9.

    Dam, M. T., Nguyen, V. T., & Lee, J.-G. (2019). A carry chain-based ADMFC design on an FPGA for EMI reduction and noise compensation. Journal of Circuits, Systems and Computers,28(01), 1950018.

    Article  Google Scholar 

  10. 10.

    Alsuraisry, H., Cheng, J.-H., Lin, J.-A., Kuo, Y.-H., Tsai, J.-H., & Huang, T.-W. (2017). A 6-GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA-III applications. Microwave and Optical Technology Letters,59(3), 622–624.

    Article  Google Scholar 

  11. 11.

    De Caro, D., De Martino, M., Petra, N., & Strollo, A. G. M. (2016). Analysis of spread-spectrum clocking modulations under synchronization timing constraint. Applications in electronics pervading industry, environment and society (pp. 153–159). Cham: Springer.

    Google Scholar 

  12. 12.

    Bae, S.-G., Hwang, S., Song, J., Lee, Y., & Kim, C. (2018). A ΔΣ modulator-based spread-spectrum clock generator with digital compensation and calibration for phase-locked loop bandwidth. IEEE Transactions on Circuits and Systems II: Express Briefs,66(2), 192–196.

    Article  Google Scholar 

  13. 13.

    Elkholy, A., Saxena, S., Shu, G., Elshazly, A., & Hanumolu, P. K. (2018). Low-jitter multi-output all-digital clock generator using DTC-based open loop fractional dividers. IEEE Journal of Solid-State Circuits,53(6), 1806–1817.

    Article  Google Scholar 

  14. 14.

    Ahmad, F., Unruh, G., Iyer, A., Su, P.-E., Abdalla, S., Shen, B., et al. (2017). A 0.5–9.5-GHz, 1.2-μs lock-time fractional-N DPLL with ± 1.25%UI period jitter in 16-nm CMOS for dynamic frequency and core-count scaling. IEEE Journal of Solid-State Circuits,52(1), 21–32.

    Article  Google Scholar 

  15. 15.

    Chen, L.-M., Yu, Z.-H., Chen, C.-Y., Hu, X.-Y., Fan, J., Yang, J., et al. (2015). A 1-V 1.2-mA fully integrated SoC for digital hearing aids. Microelectronics Journal,46(1), 12–19.

    Article  Google Scholar 

  16. 16.

    Chen, C., & Chen, L. (2019). A 79-dB SNR 1.1-mW fully integrated hearing aid SoC. Circuits, Systems, and Signal Processing,38(7), 2893–2909.

    Article  Google Scholar 

  17. 17.

    Kim, S.-W., Kim, M.-J., & Kim, J.-S. (2019). High-performance DSP platform for digital hearing aid SoC with flexible noise estimation. IET Circuits, Devices and Systems,13(5), 717–722.

    Article  Google Scholar 

  18. 18.

    Ziboon, H. T., & Azzawi, H. M. (2009). DWA technique to improve DAC of sigma-delta fractional-N frequency synthesizer for wimax. Al-Nahrain Journal of Science,12(2), 93–100.

    Google Scholar 

  19. 19.

    Thiagarajan, M., Natarajan, J., & Sharavanaraju, K. M. (2018). Pitch-based voice activity detection for feedback cancellation and noise reduction in hearing aids. Circuits, Systems, and Signal Processing,37(10), 4504–4526.

    Article  Google Scholar 

  20. 20.

    Lai, Y.-H., Chen, F., & Tsao, Y. (2017). Adaptive dynamic range compression for improving envelope-based speech perception: Implications for cochlear implants. Emerging technology and architecture for big-data analytics (pp. 191–214). Cham: Springer.

    Google Scholar 

Download references

Author information



Corresponding author

Correspondence to P. Meenakshi Vidya.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Meenakshi Vidya, P., Sudha, S. Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction. Analog Integr Circ Sig Process (2020).

Download citation


  • Hearing aid SoC
  • Analog front-end (AFE)
  • Fractional dividers (FDIV)
  • DSP platform
  • Noise reduction (NR)