A highly reliable design for two-way binary-Gray codes transformation


In this study, we design two-way binary-Gray codes encoding/decoding circuit. Two-way means that the circuit can be function programmed as either binary-to-Gray or Gray-to-binary code transformations. A self-checking capability is also embedded in circuit design to enhance the function reliability. The proposed circuit will automatically detect the error due to single-fault occurred in chip internal. Thus, the reliability of the circuit operation is further improved. After the related EDA software simulations, the error self-checking capability and two-way encoding/decoding functions are successfully verified. After simulations, the code transformations are with self-checking and bit-expandable capabilities. The proposed circuit not only improves the operation speed but also reduces the duplicate logic hardware. The concept of carry-select adder (CSA) and add-one circuit are extended in the study to reduce the signal time delay. Based on the technique of two-rail checking code, the circuit is successfully arrived for single fault detectable. By using TSMC CMOS 0.18-μm technology, an experimental chip working in 1.8 V 25 Mb data rate is realized to verify the coding function and fault self-checking capability.

This is a preview of subscription content, log in to check access.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21


  1. 1.

    International Technology Roadmap for Semiconductors (ITRS) 2.0, Executive Report, 2015.

  2. 2.

    Ensan, S. S., Moaiyeri, M. H., Moghaddam, M., & Hessabi, S. (2019). A low-power single-ended SRAM in FinFET technology. AEU-International Journal of Electronics and Communications,99, 361–368.

    Article  Google Scholar 

  3. 3.

    Sabetzadeh, F., Moaiyeri, M. H., & Ahmadinejad, M. (2019). A majority-based imprecise multiplier for ultra-efficient approximate image multiplication. IEEE Transactions on Circuits and Systems I: Regular Papers,66(11), 4200–4208.

    Article  Google Scholar 

  4. 4.

    Gray, F. (1953). “Pulse code communication,” US. Patent 2,632,058, March 17, 1953.

  5. 5.

    Doran, R. W. (2007). The Gray code. Journal of Universal Computer Science,13(11), 1573–1597.

    MathSciNet  Google Scholar 

  6. 6.

    Koehler, D. (1965). A 110-megabit gray-code to binary-code serial translator. In Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pp. 84–85.

  7. 7.

    Wang, M.C., & Camden, N.J. (1968). Conversion from Gray code to binary code. US. Patent 3,373,421, March 12, 1968.

  8. 8.

    Takizawa, K., & Okada, M. (1978). High-speed gray-binary and binary-Gray code convertors using electro-optic light modulators. Electronics Letters,14(22), 708–710.

    Article  Google Scholar 

  9. 9.

    Gayen, D. K., Chattopadhyay, T., Das, M. K., Roy, J. N., & Pal, R. K. (2011). All-optical binary to Gray code and Gray to binary code conversion scheme with the help of semiconductor optical amplifier-assisted Sagnac switch. IET Circuits, Devices and Systems,5(2), 123–131.

    Article  Google Scholar 

  10. 10.

    Singh, B., Singh, R.K., & Gangwar, S.P. (2016). Design and simulation of optical ex-OR gate and binary to gray code converter using semiconductor optical amplifier. In International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES–16), pp. 314–317.

  11. 11.

    Spargo, J. W., Jewett, R. E., & Van Duzer, T. (1983). A pipelined gray code-to-natural binary decoder for use in a Josephson A/D converter. IEEE Transactions on Magnetics,19(3), 1255–1258.

    Article  Google Scholar 

  12. 12.

    Gope, J., Bhadra, S., Laskar, S., Saha, S., Gupta, D., Adgiri, A., et al. (2017). Hybrid CMOS SET based gray to binary code converter. In 4th International Conference on Opto-Electronics and Applied Optics (Optronix), 2017.

  13. 13.

    Chakrabarty, R., Banerjee, A., Mahato, D. K., Choudhuri, S., & Mandal, N. K. (2018). Design of binary to Gray code converter for error correction in communication systems using layered quantum dot cellular automata. In 2nd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech).

  14. 14.

    Chan, H.-P. (2017). A high-speed encoding module for Gray and binary codes transformation. Master Thesis, Department of Electronic Engineering, National Chin-Yi University of Technology.

  15. 15.

    Chang, T. Y., & Hsiao, M. J. (1998). Carry-select adder using single-ripple-carry adder. Electronics Letters,34(22), 2101–2103.

    Article  Google Scholar 

  16. 16.

    Lo, J. C. (1993). A novel area-time efficient static CMOS totally self-checking comparator. IEEE Journal of Solid-State Circuits,28(2), 165–168.

    Article  Google Scholar 

  17. 17.

    Vasudevan, D. P., Lalaand, P. K., & Parkerson, J. P. (2007). Self-checking carry-select adder design based on two-rail encoding. IEEE Transactions on Circuits and Systems I: Regular Papers,54(12), 2696–2705.

    Article  Google Scholar 

  18. 18.

    Chen, W.-C. (2011). Design of self-repair carry select adder. Master Thesis, Department of Electronic Engineering, National Chin-Yi University of Technology.

  19. 19.

    Bui, H. T., Wang, Y., & Jiang, Y. (2002). Design and analysis of low-power 10-transistor full adders using novel xor–xnor gates. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing,49(1), 25–30.

    Article  Google Scholar 

Download references


This work was funding part supported by the Ministry of Science and Technology Project (MOST 105-2221-E-167-022), and EDA tools support, experimental CMOS processes and chip fabricated, Taiwan Semiconductor Research Institute (TSRI) and Taiwan Semiconductor Manufactory Corp. (tsmc).

Author information




F.-T.C and Y.-C.H conceived and designed this study after co-discussion; F.-T.C performed CAD tool simulations and the experiments chip measured; Y.-C.H and C.-K.T analyzed the data and wrote/organized the paper.

Corresponding author

Correspondence to Yu-Cherng Hung.

Ethics declarations

Conflict of interest:

The authors declare no conflict of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Cheng, F., Hung, Y. & Tung, C. A highly reliable design for two-way binary-Gray codes transformation. Analog Integr Circ Sig Process 104, 81–92 (2020). https://doi.org/10.1007/s10470-020-01653-6

Download citation


  • Self-checking
  • Binary code
  • Gray code
  • Two-rail code
  • Built-in self-test