Abstract
In this work, we demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower cross-coupled transistors and then inject the source terminals of the upper cross-coupled transistors. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower cross-coupled transistors. Due to the strong second harmonic signal (2finj) at the source terminals of the upper cross-coupled transistors, there are notable locked fundamental signals (finj) at the drain terminals of the upper cross-coupled transistors. ILFD31 occupies a chip area of 0.744 × 0.859 mm2 (i.e. 0.639 mm2), consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5–95.9 GHz). ILFD32 occupies a chip area of 0.87 × 0.775 mm2 (i.e. 0.674 mm2), consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8–109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s.
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Acknowledgements
This work is supported by the Ministry of Science and Technology (MOST) of the R.O.C. under Contracts MOST105-2221-E-260-025-MY3 and MOST106-2221-E-260-025-MY2. The authors are very grateful for the supports from the National Chip Implementation Center (CIC), Taiwan, for chip fabrication, and National Nano-Device Laboratory (NDL), Taiwan, for measurements.
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Lin, YS., Lan, KS. Low power W-band divide-by-3 injection-locked frequency dividers with wide locking range in 90 nm CMOS. Analog Integr Circ Sig Process 99, 177–189 (2019). https://doi.org/10.1007/s10470-019-01403-3
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DOI: https://doi.org/10.1007/s10470-019-01403-3