Analog Integrated Circuits and Signal Processing

, Volume 96, Issue 3, pp 555–564 | Cite as

A low-noise small-area operational amplifier using split active-feedback compensation technique

  • Ippei Akita
  • Hicham Haibi
  • Makoto Ishida


A low-noise small-area three-stage operational amplifier is presented for arrayed sensor interface systems. The designed amplifier employs a novel small-area phase compensation scheme that allows a relatively high transconductance in the first stage, resulting in relatively low input-referred noise. The proposed amplifier implemented in a standard 180-nm CMOS process occupies an active area of only 0.015 \(\mathrm{mm}^2\). The measurement results show that the amplifier achieves a 6.2-MHz gain-bandwidth product, an input-referred noise of 27 nV/\(\surd \)Hz, and a phase margin of 60°. The current dissipation is 177 \(\upmu \)A at a power supply of 1.5 V.


Operational amplifier Low noise Small area Active-feedback compensation 



This work was supported in part by JSPS Grant-in-Aid for Scientific Research (15H05525 and 25820141). We would like to express our thanks to Rohm Corp., Toppan Printing Corp., and Cadence Design Systems Inc. and Mentor Graphics Inc. through the VLSI Design and Education Center (VDEC), the University of Tokyo, for chip fabrication and EDA tools.


  1. 1.
    Uddin, A., Milaninia, K., Chen, C. H., & Theogarajan, L. (2011). Wafer scale integration of CMOS chips for biomedical applications via self-aligned masking. IEEE Transactions on Components, Packaging and Manufacturing Technology, 1(12), 1996–2004.CrossRefGoogle Scholar
  2. 2.
    Holleman, J., Zhang, F., & Otis, B. (2011). Ultra low-power integrated circuit design for wireless neural interfaces. Berlin: Springer.CrossRefGoogle Scholar
  3. 3.
    Harrison, R. R. (2008). The design of integrated circuits to observe brain activity. Proceedings of the IEEE, 96(7), 1203–1216.CrossRefGoogle Scholar
  4. 4.
    Aziz, J. N., Abdelhalim, K., Shulyzki, R., Genov, R., Bardakjian, B. L., Derchansky, M., et al. (2009). 256-channel neural recording and delta compression microsystem with 3D electrodes. IEEE Journal of Solid-State Circuits, 44(3), 995–1005.CrossRefGoogle Scholar
  5. 5.
    Akita, I., & Ishida, M. (2013). A 0.06 mm\(^2\) 14 nV/\(\surd \)Hz chopper instrumentation amplifier with automatic differential-pair matching. In 2013 IEEE international solid-state circuits conference digest of technical papers (ISSCC) (pp. 178–179). IEEE.Google Scholar
  6. 6.
    Uranga, A., Navarro, X., & Barniol, N. (2004). Integrated CMOS amplifier for ENG signal recording. IEEE Transactions on Biomedical Engineering, 51(12), 2188–2194.CrossRefGoogle Scholar
  7. 7.
    Annema, A. J., Nauta, B., Van Langevelde, R., & Tuinhout, H. (2005). Analog circuits in ultra-deep-submicron CMOS. IEEE Journal of Solid-State Circuits, 40(1), 132–143.CrossRefGoogle Scholar
  8. 8.
    Dautriche, P. (2011). Analog design trends and challenges in 28 and 20 nm CMOS technology. In 2011 Proceedings of ESSCIRC (ESSCIRC) (pp. 1–4). IEEE.Google Scholar
  9. 9.
    Vertregt, M. (2006). The analog challenge of nanometer CMOS. In International electron devices meeting, 2006 (IEDM’06) (pp. 1–8). IEEE.Google Scholar
  10. 10.
    Guo, S., & Lee, H. (2009). Single-capacitor active-feedback compensation for small-capacitive-load three-stage amplifiers. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(10), 758–762.CrossRefGoogle Scholar
  11. 11.
    Yan, Z., Mak, P. I., Law, M. K., & Martins, R. P. (2013). A 0.016-mm\(^2\) 144-μW three-stage amplifier capable of driving 1-to-15 nF capacitive load with \(>\)0.95-MHz GBW. IEEE Journal of Solid-State Circuits, 48(2), 527–540.CrossRefGoogle Scholar
  12. 12.
    Guo, S., & Lee, H. (2011). Dual active-capacitive-feedback compensation for low-power large-capacitive-load three-stage amplifiers. IEEE Journal of Solid-State Circuits, 46(2), 452–464.CrossRefGoogle Scholar
  13. 13.
    Leach, W. M. (1994). Fundamentals of low-noise analog circuit design. Proceedings of the IEEE, 82(10), 1515–1538.CrossRefGoogle Scholar
  14. 14.
    Haibi, H., Akita, I., & Ishida, M. (2013). A 27-n/\(\surd \)Hz 0.015-mm\(^2\) three-stage operational amplifier with split active-feedback compensation. In 2013 IEEE Asian solid-state circuits conference (A-SSCC) (pp. 365–368). IEEE.Google Scholar
  15. 15.
    Carusone, T. C. et al. (2012). Analog integrated circuit design. Columbia Law Review Association Harvard Law Review Association.Google Scholar
  16. 16.
    Razavi, B. (2001). Design of analog CMOS integrated circuits. New York: McGraw-Hill.Google Scholar
  17. 17.
    Enz, C. C., & Temes, G. C. (1996). Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization. Proceedings of the IEEE, 84(11), 1584–1614.CrossRefGoogle Scholar
  18. 18.
    Palumbo, G., & Pennisi, S. (2002). Design methodology and advances in nested-Miller compensation. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 49(7), 893–903.CrossRefGoogle Scholar
  19. 19.
    Akita, I., & Ishida, M. (2014). A chopper-stabilized instrumentation amplifier using area-efficient self-trimming technique. Analog Integrated Circuits and Signal Processing, 81(3), 571–582.CrossRefGoogle Scholar
  20. 20.
    Steyaert, M. S., & Sansen, W. M. (1987). A micropower low-noise monolithic instrumentation amplifier for medical purposes. IEEE Journal of Solid-State Circuits, 22(6), 1163–1168.CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electrical and Electronic Information EngineeringToyohashi University of TechnologyToyohashiJapan

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