Ultra-low-power bulk-driven fully differential subthreshold OTAs with partial positive feedback for Gm-C filters
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This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA1 and (1:4) in OTA2. The OTA2 offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency Gm-C filter suitable for bio-signal applications. The proposed OTA2 has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of − 72 dB, for 1.2 Vp–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA1.
KeywordsOperational transconductance amplifier (OTA) Bulk-driven Source-degeneration Flipped voltage follower Subthreshold region Composite self cascode Biquadratic Gm-C filter
This work has been performed using the resources of VLSI laboratories of ECE and EE Departments in Cadence Spectre UMC 0.18 μm CMOS process technology environment, developed under TEQIP-II project funded by Department of Information Technology, Ministry of Communication and Information Technology Government of India at NERIST, Nirjuli, Arunachal Pradesh, 791109, India. The authors appreciate the help provided by Tanmay Dubey in learning the layout design aspects of cadence tool in its UMC library file, during revision process of this manuscript. The authors further, appreciate the valuable comments of the reviewers which has improved this manuscript.
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Conflict of interest
The authors declare that they have no conflict of interest regarding the publication of this paper.
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