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A power management system architecture for LF passive RFID tags

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Abstract

This paper presents a low power, low voltage power management (PM) system for low-frequency passive RFID tags in a standard CMOS 0.18 µm technology. Passive tags have no internal power source but use the incoming RF energy transmitted by a transceiver to power all the circuitry inside them via a rectifier. Due to the wide variation of the rectified voltage as a function of the RF power, two stages of regulation are required: a shunt regulator working as limiter (3 V) at the rectifier output, and a LDO regulator at a tighter range of 1.15 V. Besides that, two blocks monitor the available RF power at the LDO regulated output and flag when the power is low for different tag operation modes: power-on reset during a read event, and power flag during a write event. All blocks rely on a low power resistor-less 3.5 nA current reference and a 400 mV voltage reference. Both references make use of the self cascode MOSFET structure. The complete PM system is functional with 2 µA current.

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Acknowledgments

The authors would like to acknowledge the contributions of the fellow members of the CEITEC design team.

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Authors and Affiliations

  1. Design Center - CEITEC S.A. Semiconductors, Porto Alegre, Brazil

    Fernando Paixão Cortes, Juan Pablo Martinez Brito, Everton Ghignatti Jr., Alfredo Olmos, Fernando Chavez & Marcelo Lubaszewski

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  1. Fernando Paixão Cortes
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  2. Juan Pablo Martinez Brito
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  3. Everton Ghignatti Jr.
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  4. Alfredo Olmos
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  5. Fernando Chavez
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  6. Marcelo Lubaszewski
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Correspondence to Fernando Paixão Cortes.

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Cortes, F.P., Brito, J.P.M., Ghignatti, E. et al. A power management system architecture for LF passive RFID tags. Analog Integr Circ Sig Process 85, 47–55 (2015). https://doi.org/10.1007/s10470-015-0598-8

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  • DOI: https://doi.org/10.1007/s10470-015-0598-8

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