Compact and power efficient SEC-DED codec for computer memory


Frequently, soft errors occur due to striking of radioactive particles in memory cells which reduce the reliability of memory systems. Generally, single error correction-double error detection (SEC-DED) codes are employed to detect and correct the soft errors in semiconductor memory systems. In this paper, a new optimization algorithm is proposed based on common sub-expression elimination method. By employing this proposed optimization algorithm, more simplified expressions for encoder and decoder are obtained from parity check matrix (H-matrix). Proposed optimization technique has been used to implement seven different SEC-DED codecs with message length of 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits and 512 bits. Compact design requires at most 21.66% lesser number of two-input XOR gates compared to related SEC-DED codes. All codec architectures are simulated and synthesized using both FPGA and ASIC platforms. Area and power consumption of proposed designs are reduced compared to the existing design without affecting its speed. Proposed designs are beneficial in computer memory systems due to its compactness and lower power consumption.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7


  1. Argyrides CA, Reviriego P, Pradhan DK, Maestro JA (2010) Matrix-based codes for adjacent error correction. IEEE Trans Nuclear Sci 57(4):2106–2111

    Article  Google Scholar 

  2. Bajura MA, Boulghassoul Y, Naseer R, Das Gupta S, Witulski AF, Sondeen J, Stansberry SD, Draper J, Massengill LW, Damoulakis JN (2007) Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs. IEEE Trans Nucl Sci 54(4):935–945

    Article  Google Scholar 

  3. Baumann R (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans Device Mater Reliab 5(3):305–316

    Article  Google Scholar 

  4. Cha S, Yoon H (2012) Efficient implementation of single error correction and double error detection code with check bit pre-computation for memories. JSTS 12(4):418–425

    Article  Google Scholar 

  5. Chen CL, Hsiao MY (1984) Error-correcting codes for semiconductor memory applications: a state-of-the-art review. IBM J Res Dev 28(2):124–134

    Article  Google Scholar 

  6. Demirci M, Reviriego P, Maestro JA (2016) Implementing double error correction orthogonal latin squares codes in SRAM-based FPGAs. Microelectron Reliab 56:221–227

    Article  Google Scholar 

  7. Dutta A, Touba NA (2007) Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code. In: 25th IEEE VLSI test symposium (VTS’07), pp 349–354

  8. Gherman V, Evain S, Seymour N, Bonhomme N (2011) Generalized parity-check matrices for SEC-DED codes with fixed parity. In: Proceedings of IEEE on-line testing symposium, pp 198–201

  9. Hamming RW (1950) Error detecting and error correcting codes. Bell Syst Tech J 29(2):147–160

    MathSciNet  Article  Google Scholar 

  10. Hsiao MY (1970) A class of optimal minimum odd-weight column SEC-DED codes. IBM J Res Dev 14(4):395–401

    Article  Google Scholar 

  11. Kang SH, Park IC (2006) Loosely coupled memory-based decoding architecture for low density parity check codes. IEEE Trans Circ Syst I: Regul Pap 53(5):1045–1056

    MathSciNet  Article  Google Scholar 

  12. Liu S, Reviriego P, Xiao L, Maestro JA (2017) A method to recover critical bits under a double error in SEC-DED protected memories. Microelectron Reliab 73:92–96

    Article  Google Scholar 

  13. Ming Z, Yi XL, Wei LH (2011) New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory. In: 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, IEEE, pp 254–259

  14. Namba K, Lombardi F (2018) A single and adjacent error correction code for fast decoding of critical bits. IEEE Trans Comput 67(10):1525–1531

    MathSciNet  Article  Google Scholar 

  15. Naseer R, Draper J (2008) Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs. In: ESSCIRC 2008–34th European Solid-State Circuits Conference, IEEE, pp 222–225

  16. Neale A, Sachdev M (2013) A new SEC-DED error correction code subclass for adjacent MBU tolerance in embedded memory. IEEE Trans Device Mater Reliab 13(1):223–230

    Article  Google Scholar 

  17. Penzo L, Sciuto D, Silvano C (1995) Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems. IEEE Trans Inf Theory 41(2):584–591

    Article  Google Scholar 

  18. Pontarelli S, Reviriego P, Ottavi M, Maestro JA (2015) Low delay single symbol error correction codes based on reed solomon codes. IEEE Trans Comput 64(5):1497–1501

    MathSciNet  Article  Google Scholar 

  19. Rastogi A, Agarawal M, Gupta B (2009) SEU MITIGATION-using 1/3 rate convolution coding. In: 2009 2nd IEEE International Conference on Computer Science and Information Technology, IEEE, pp 180–183

  20. Reviriego P, Maestrom JA, Baeg S, Wen S, Wong R (2010) Protection of memories suffering MCUs through the selection of the optimal interleaving distance. IEEE Trans Nucl Sci 57(4):2124–2128

    Article  Google Scholar 

  21. Reviriego P, Pontarelli S, Maestro JA, Ottavi M (2013) A method to construct low delay single error correction codes for protecting data bits only. IEEE Trans Comput Aided Design Integr Circ Syst 32(3):479–483

    Article  Google Scholar 

  22. Reviriego P, Martínez J, Pontarelli S, Maestro JA (2014) A method to design SEC-DED-DAEC codes with optimized decoding. IEEE Trans Device Mater Reliab 14(3):884–889

    Article  Google Scholar 

  23. Reviriego P, Demirci M, Evans A, Maestro JA (2016a) A method to design single error correction codes with fast decoding for a subset of critical bits. IEEE Trans Circuits Syst II Express Briefs 63(2):171–175

    Article  Google Scholar 

  24. Reviriego P, Liu SS, Sánchez-Macián A, Xiao L, Maestro JA (2016b) Unequal error protection codes derived from SEC-DED codes. Electron Lett 52(8):619–620

    Article  Google Scholar 

  25. Richter M, Oberlaender K, Goessel M (2008) New linear SEC-DED codes with reduced triple bit error miscorrection probability. In: Proc. of IEEE on-line testing symp., pp 37–42

  26. Saleh AM, Serrano JJ, Patel JH (1990) Reliability of scrubbing recovery-techniques for memory systems. IEEE Trans Reliab 39(1):114–122

    Article  Google Scholar 

  27. Satoh S, Tosaka Y, Wender SA (2000) Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM’s. IEEE Electron Device Lett 21(6):310–312

    Article  Google Scholar 

  28. Tsiligiannis G, Dilillo L, Bosio A, Girard P, Pravossoudovitch S, Todri A, Virazel A, Puchner H, Frost C, Wrobel F, Saigne F (2014) Multiple cell upset classification in commercial SRAMs. IEEE Trans Nucl Sci 61(4):1747–1754

    Article  Google Scholar 

  29. Wei W, Namba K, Kim YB, Lombardi F (2016) A novel scheme for tolerating single event/multiple bit upsets (SEU/MBU) in non-volatile memories. IEEE Trans Comput 1:1

    MathSciNet  MATH  Google Scholar 

Download references


Authors would like to thank SMDP-C2SD, University of Calcutta for providing Cadence simulation software. Authors also like to thank reviewers for their valuable comments to improve the quality of this paper.

Author information



Corresponding author

Correspondence to Jagannath Samanta.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Samanta, J., Bhaumik, J. & Barman, S. Compact and power efficient SEC-DED codec for computer memory. Microsyst Technol 27, 359–368 (2021).

Download citation