Compact and power efficient SEC-DED codec for computer memory

Abstract

Frequently, soft errors occur due to striking of radioactive particles in memory cells which reduce the reliability of memory systems. Generally, single error correction-double error detection (SEC-DED) codes are employed to detect and correct the soft errors in semiconductor memory systems. In this paper, a new optimization algorithm is proposed based on common sub-expression elimination method. By employing this proposed optimization algorithm, more simplified expressions for encoder and decoder are obtained from parity check matrix (H-matrix). Proposed optimization technique has been used to implement seven different SEC-DED codecs with message length of 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits and 512 bits. Compact design requires at most 21.66% lesser number of two-input XOR gates compared to related SEC-DED codes. All codec architectures are simulated and synthesized using both FPGA and ASIC platforms. Area and power consumption of proposed designs are reduced compared to the existing design without affecting its speed. Proposed designs are beneficial in computer memory systems due to its compactness and lower power consumption.

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Acknowledgements

Authors would like to thank SMDP-C2SD, University of Calcutta for providing Cadence simulation software. Authors also like to thank reviewers for their valuable comments to improve the quality of this paper.

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Correspondence to Jagannath Samanta.

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Samanta, J., Bhaumik, J. & Barman, S. Compact and power efficient SEC-DED codec for computer memory. Microsyst Technol 27, 359–368 (2021). https://doi.org/10.1007/s00542-019-04366-7

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