Skip to main content
SpringerLink
Log in

Effective resistance calculation and automated solution for fixing reliability verification violations

  • Technical Paper
  • Published:
Microsystem Technologies Aims and scope Submit manuscript

Abstract

This paper covers the automation done to upgrade the reliability verification in the backend circuit design of microchips. Automation is done to upgrade the reduction of violations which occurs during the reliability verification flow by considering each branch or loop resistors and calculating the current through each resistor. It is also estimated that number of straps required particularly for via 3 and via 4 violations so that to reduce number of RV flow execution. Automation is extremely basic in enhancing the proficiency of plan and assembling phases of a VLSI product. This paper gives a flow, which enhances the efficiency of effective resistance thereby improves the proficiency of reliability verification. This reliability verification (RV) analysis flow, can be invoked post Routing of the plan and encourages the VLSI designers to recognize the adjustments in current design, that caused the signal scaling factors (SF)/self-heat violations from past one. This automation essentially decreases SF/self-heat in the circuit by reducing the resistance, in this way decreasing the back end configuration time.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3

(courtesy http://www.google.co.in)

Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

(courtesy http://www.google.co.in)

Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  • Nicollian PE, Hunter WR, Hu JC (2000) Experimental evidence for voltage driven breakdown models in ultra-thin gate oxides. In Proceedings of the IEEE international reliability physics symposium, San Jose, CA, pp 7–15,

  • Ogawa ET, Ki-Don Lee VA, Blaschke PS Ho (2002) Electromigration reliability issues in dual-damascene Cu interconnections. Proc IEEE Trans Reliab 51(4):403–419

    Article  Google Scholar 

  • Shinkai K, M Hashimoto, Onoye T (2007) Future prediction of self-heating in short intra-block wires. In: 8th international symposium on quality electronic design, pp 660–665

  • Suehle JH (2002) Ultrathin gate oxide reliability: physical models, statistics, and characterization. IEEE Trans Electron Devices 49(6):958–971

    Article  Google Scholar 

  • Yuan T, Ning TH (2013) Fundamentals of modern VLSI devices, 2nd edn. Cambridge University Press, Cambridge

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. VLSI and Embedded Systems, R.V.C.E., Bengaluru, 59, India

    M. M. Mohammed Imran

  2. Department of ECE, R.V.C.E., Bengaluru, 59, India

    N. Shylashree

Authors
  1. M. M. Mohammed Imran
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. N. Shylashree
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to N. Shylashree.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Imran, M.M.M., Shylashree, N. Effective resistance calculation and automated solution for fixing reliability verification violations. Microsyst Technol 24, 4817–4824 (2018). https://doi.org/10.1007/s00542-018-3886-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00542-018-3886-2

Search

Navigation