Abstract
This paper presents FPGA implementation of retimed high speed adaptive filter structures for speech enhancement. In this work, various high speed adaptive filtering structures for noise cancellation are implemented for Xilinx Spartan-6 series and Virtex-4 series FPGA platforms. It has been observed that various VLSI implementations vary considerably in clock speed, hardware requirements, latency and cost. For instance, for the Spartan-6 series FPGA platform implementation, the clock speed of retimed DF-RDLMS implementation is found to be 98.309 MHz whereas that of conventional unretimed DF-LMS structure is 85.485 MHz, thereby having an improvement of 15% in clock speed. Similarly, for the Virtex-4 series FPGA platform implementation, the clock speed of retimed DF-RDLMS implementation is found to be 88.176 MHz whereas that of conventional unretimed DF-LMS structure is 75.855 MHz, thereby having an improvement of 16.5% in clock speed. The VLSI implementation and the performance analysis provides crucial information about an algorithm structure such as hardware requirements, power consumption and real-time performance. Performance of the implemented structures have been checked in terms of operating frequency, maximum combinational path delay, latency, and power consumption.
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References
Bahoura M, Ezzaidi H (2010) FPGA-implementation of wavelet-based denoising technique to remove power-line interference from ECG signal. In: 10th IEEE international conference on information technology and applications in biomedicine (ITAB), Corfu, Greece, pp 1–4
Bahoura M, Ezzaidi H (2011) FPGA implementation of parallel and sequential architectures for adaptive noise cancellation. In: Circuits, systems and signal processing, vol 30, pp 1521–1548. Springer, SP Birkhäuser Verlag Boston
Dai J, Wang Y (2010) NLMS adaptive algorithm implement based on FPGA. In: Third international conference on intelligent networks and intelligent systems, IEEE, 2010, Shenyang, China, pp 422–425. https://doi.org/10.1109/icinis.2010.97
Dhal M, Ghosh M, Goel P, Kar A, Mohapatra S, Chandra M (2015) A unique adaptive noise canceller with advanced variable-step BLMS algorithm. In: 2015 international conference on advances in computing communications and informatics (ICACCI) Kochi, India, pp 178–183
Elhossini A, Areibi S, Dony R (2006) An FPGA implementation of the LMS adaptive filter for audio processing. In: IEEE International Conference on Reconfigurable Computing and FPGA’s, 2006. ReConFig 2006. IEEE, San Luis Potosi, Mexico, pp 1–8
Fohl W, Matthies J (2009) A FPGA based adaptive noise cancelling system. In: Proceedings of the 12th international conference on digital audio effects (DAFX-09), Como, Italy, September 01–04
Haykin S (2008) Adaptive filter theory, 4th edn. Pearson, India
Kar A, Chanda AP, Mohapatra S, Chandra M (2014) An improved filtered-x least mean square algorithm for acoustic noise suppression. In: Advanced computing, networking and informatics-volume 1, smart innovation, systems and technologies, vol 27. Springer, Cham, pp 25–32
Long G, Ling F, Proakis JG (1989) The LMS algorithm with delayed coefficient adaptation. IEEE Trans Acoust Speech Signal Process 37(9):1397–1405
Mohanty BK, Singh G, Panda G (2017) Hardware design for VLSI implementation of FxLMS- and FsLMS-based active noise controllers. Circuits Syst Signal Process (Springer) 36(2):447–473 (first online April 2016)
Monteiro J, Devadas S, Ghosh A (1993) Retiming sequential circuits for low power. In: Proceedings of international conference on computer aided design (ICCAD-1993), Santa Clara, California, Nov 7–11, 1993, pp 398–402
Mustafa R, Umat C, Ali MAM, Al-asady AD (2009) Design and implementation of least mean square adaptive filter on altera cyclone II field programmable gate array for active noise control. In: IEEE Symposium on Industrial Electronics & Applications (ISIEA 2009), vol 1, Kuala Lumpur, Malaysia, pp 479–484
Parhi KK (2010) VLSI digital Signal processing systems: design and implementation, 1st edn. Wiley, India
Rizwan S (2008) Retimed decomposed serial Berlekamp–Massey (BM) architecture for high-speed Reed–Solomon decoding. In: 21st international conference on VLSI design (VLSID 2008), Hyderabad, India, pp 53–58
Samudravijaya K, Rao PVS, Agrawal SS (2000) Hindi speech database. In: Proceedings of international conference on spoken language processing, vol 4. ICSLP-2000, Beijing, China, pp 456–459
Shenming W, Suntiamorntut W, Jindapetch N, Qiufan J (2011) Scheduling and resources sharing technique for adaptive LMS filter. In: The 8th electrical engineering/electronics computer telecommunications and information technology (ECTI) association of Thailand, conference 2011, pp 114–117
Yagain D, Krishna AV, Chennapnoor S (2012) Design optimization platform for synthesizable high speed digital filters using retiming technique. In: 2012 10th IEEE international conference on semiconductor electronics (ICSE), Kuala Lumpur, Malaysia, pp 551–555
Yi Y, Woods R (2005) High speed FPGA-based implementations of delayed-LMS filters. J VLSI Signal Process 39:113–131
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Goel, P., Chandra, M. VLSI implementations of retimed high speed adaptive filter structures for speech enhancement. Microsyst Technol 24, 4799–4806 (2018). https://doi.org/10.1007/s00542-018-3884-4
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DOI: https://doi.org/10.1007/s00542-018-3884-4