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Analyses and statistics of the electrical fail for flip chip packaging by using ANSYS simulation software and really underfill materials

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Abstract

ANSYS simulation software has gold standard for modeling and simulating surface chemistry reactions that are used for the conceptual development of combustion systems in chemical and materials processing equipment. In this study, three different models of the solder bumps were arranged, designed, and simulated by ANSYS simulation software. The first model was a single solder bump, which had the height of 70 µm and diameter of 115 µm, and the both diameters to contact upper chip and lower substrates were 90 µm. The second model was that the single solder bumps were arranged to form an array with different spacing between two “single solder bumps”, the area and height were 1520 μm × 3610 μm and 70 μm. The third model was that the single solder bumps with two different arranged arrays were formed on the substrates on different sides, the distances between two “single solder bumps” had different values in the two arranged arrays, and the area and height for this model were 2600 μm × 2570 μm and 70 μm. We would use five differently underfill materials with different properties (including viscosity) as the simulated parameters in the third model. Finally, the five underfill materials were used in the dispensing experiment to find the optimum one for the flip chip packaging.

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Acknowledgements

The authors would like to acknowledge the financial supports of the projects with the nos. of MOST 106-2221-E-390-019 and MOST 105-2622-E-390-003-CC3.

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Authors and Affiliations

  1. Department of Economics and Management, Ningde Normal University, Ningde, China

    Shang-Te Tsai

  2. Department of Aero-Electronic Engineering, Air Force Institute of Technology, Kaohsiung, 820, Taiwan, ROC

    Chi-Yu Lin

  3. Department of Electrical Engineering, National University of Kaohsiung, Kaohsiung, 811, Taiwan, ROC

    Sung-Mao Wu & Chung-Yao Chang

  4. Department of Chemical and Materials Engineering, National University of Kaohsiung, Kaohsiung, 811, Taiwan, ROC

    Cheng-Fu Yang

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  1. Shang-Te Tsai
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  2. Chi-Yu Lin
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  5. Cheng-Fu Yang
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Correspondence to Cheng-Fu Yang.

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Tsai, ST., Lin, CY., Wu, SM. et al. Analyses and statistics of the electrical fail for flip chip packaging by using ANSYS simulation software and really underfill materials. Microsyst Technol 24, 4017–4024 (2018). https://doi.org/10.1007/s00542-017-3605-4

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  • DOI: https://doi.org/10.1007/s00542-017-3605-4

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