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Steiner Trees with Bounded RC-Delay

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Abstract

We consider the Minimum Elmore Delay Steiner Tree Problem, which is a key problem in VLSI design: We are given a set of pins which have to be connected by a Steiner tree. One of the pins is the source. Challenging timing constraints impose tight bounds on the delay of propagating a signal from the source to the other pins. The commonly used measure is Elmore delay (Elmore in J Appl Phys 19:55–63, 1948). We consider two variants: minimizing the maximum Elmore delay or a weighted sum of Elmore delays. Both variants are strongly NP-hard even for very restricted special cases. Although it is a central problem in VLSI design (Kahng and Robins in On optimal interconnections for VLSI. Kluwer, Boston, 1995; Korte and Vygen in Building bridges—between mathematics and computer science. Springer, Berlin, pp 333–368, 2008), no approximation algorithms were known so far. In this work, we give the first constant-factor approximation algorithm. It works for both variants. The algorithm achieves an approximation ratio of 3.39 in the rectilinear plane and 4.11 in general metric spaces. We can show that our algorithm is best possible in a certain sense. We also demonstrate that our algorithm leads to improvements on real world VLSI instances compared to the currently used standard method of computing short Steiner trees.

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Notes

  1. The Hanan grid is the grid that is induced by the set of x- and y-coordinates of all terminals—see Hanan [18].

  2. The Shortest Steiner Tree Problem is the problem of finding a Steiner tree Y with l(Y) minimum. It is more commonly referred to as Minimum Steiner Tree Problem, but since in our application edge weights can most suitably be regarded as lengths, we will use this term instead.

  3. Every general Steiner tree can be transformed into such a tree in linear time by adding additional Steiner points and edges of length 0.

  4. Here we assume \(\tau = \varOmega (|V(Y_0)|)\).

  5. \(\beta \le 2\) can always be assumed by not using anything worse than a minimum spanning tree for the terminal set as initial solution.

  6. A rectilinear minimum spanning tree can be computed in \(O(|T| \log |T|)\) time using only edges of the Delaunay Triangulation.

  7. The metric closure of a graph \(G=(V,E)\) with edge lengths \(l:E \rightarrow {\mathbb {R}}_{\ge 0}\) is defined as the complete graph with vertex set V and a metric distance function dist such that dist(vw) equals the length of a shortest path between v and w with respect to l in G.

  8. The actual algorithm used depends on the size of the terminal set.

References

  1. Arora, S.: Polynomial time approximation schemes for Euclidean traveling salesman and other geometric problems. J. ACM 45, 753–782 (1998)

    Article  MathSciNet  MATH  Google Scholar 

  2. Boese, K.D., Kahng, A.B., McCoy, B.A., Robins, G.: Fidelity and near-optimality of Elmore-based routing constructions. In: IEEE International Conference on Computer Design, pp. 81–84 (1993)

  3. Boese, K.D., Kahng, A.B., McCoy, B.A., Robins, G.: Rectilinear Steiner trees with minimum Elmore delay. In: Proceedings of the 31st Annual Design Automation Conference, pp. 381–386. ACM, New York (1994)

  4. Boese, K.D., Kahng, A.B., McCoy, B.A., Robins, G.: Near-optimal critical sink routing tree constructions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14, 1417–1436 (1995)

    Article  Google Scholar 

  5. Boese, K.D., Kahng, A.B., Robins, G.: High-Performance routing trees with identified critical sinks. In: Proceedings of the 30th International Design Automation Conference, pp. 182–187 (1993)

  6. Brazil, M., Zachariasen, M.: Optimal Interconnection Trees in the Plane. Springer, Berlin (2015)

    Book  MATH  Google Scholar 

  7. Byrka, J., Grandoni, F., Rothvoss, T., Sanità, L.: Steiner tree approximation via iterative randomized rounding. J. ACM 60, 6:1–6:33 (2013)

    Article  MathSciNet  MATH  Google Scholar 

  8. Celik, M., Pileggi, L., Odabasioglu, A.: IC Interconnect Analysis. Kluwer, Boston (2002)

    Google Scholar 

  9. Chu, C., Wong, Y.C.: FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27, 70–83 (2008)

    Article  Google Scholar 

  10. Cong, J., Leung, K.S., Zhou, D.: Performance-driven interconnect design based on distributed rc delay model. In: Proceedings of the 30th International Design Automation Conference, pp. 606–611. ACM (1993)

  11. Córdova, J., Lee, Y.: A Heuristic Algorithm for the Rectilinear Steiner Arborescence Problem. Tech. rep., University of Puerto Rico, Computer Science Department (1994)

  12. Dreyfus, S., Wagner, R.: The Steiner problem in graphs. Networks 1, 195–207 (1972)

    Article  MathSciNet  MATH  Google Scholar 

  13. Elmore, W.: The transient response of damped linear networks with particular regard to wideband amplifiers. J. Appl. Phys. 19, 55–63 (1948)

    Article  Google Scholar 

  14. Garey, M.R., Johnson, D.S.: The rectilinear Steiner tree problem is NP-complete. SIAM J. Appl. Math. 32, 826–834 (1977)

    Article  MathSciNet  MATH  Google Scholar 

  15. Garey, M.R., Johnson, D.S.: Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman & Company, New York (1990)

    MATH  Google Scholar 

  16. Gester, M., Müller, D., Nieberg, T., Panten, C., Schulte, C., Vygen, J.: BonnRoute: Algorithms and data structures for fast and good VLSI routing. ACM Trans. Des. Autom. Electron. Syst. 18, 32:1–32:24 (2013)

    Article  Google Scholar 

  17. Gupta, R., Tutuianu, B., Pileggi, L.: The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16, 95–104 (1997)

    Article  Google Scholar 

  18. Hanan, M.: On Steiner’s Problem with rectilinear distance. SIAM J. Appl. Math. 14, 255–265 (1966)

    Article  MathSciNet  MATH  Google Scholar 

  19. Held, S., Korte, B., Rautenbach, D., Vygen, J.: Combinatorial optimization in VLSI design. In: Combinatorial Optimization: Methods and Applications, pp. 33–96. IOS Press, Amsterdam (2011)

  20. Held, S., Rotter, D.: Shallow-light Steiner arborescences with vertex delays. In: Proceedings of the 16th International Conference on Integer Programming and Combinatorial Optimization, pp. 229–241. Springer, Heidelberg (2013)

  21. Hwang, F.: On Steiner minimal trees with rectilinear distance. SIAM J. Appl. Math. 30, 104–114 (1976)

    Article  MathSciNet  MATH  Google Scholar 

  22. Kadodi, T.: Steiner Routing Based on Elmore Delay Model for Minimizing Maximum Propagation Delay. Master’s Thesis, Japan Advanced Institute of Science and Technology (1999)

  23. Kahng, A., Robins, G.: On Optimal Interconnections for VLSI. Kluwer, Boston (1995)

    Book  MATH  Google Scholar 

  24. Karp, R.: Reducibility among combinatorial problems. In: Miller, R., Thatcher, J. (eds.) Complexity of Computer Computations, pp. 85–103. Plenum Press, New York (1972)

    Chapter  Google Scholar 

  25. Khuller, S., Raghavachari, B., Young, N.: Balancing minimum spanning and shortest path trees. In: Proceedings of the Fourth Annual ACM-SIAM Symposium on Discrete Algorithms, pp. 243–250. Society for Industrial and Applied Mathematics, Philadelphia (1993)

  26. Korte, B., Vygen, J.: Combinatorial Optimization: Theory and Algorithms, 5th edn. Springer, Heidelberg (2012)

    Book  MATH  Google Scholar 

  27. Korte, B., Vygen, K.: Combinatorial problems in chip design. In: Grötschel, M., Katona, G.O.H. (eds.) Building Bridges—Between Mathematics and Computer Science, pp. 333–368. Springer, Berlin (2008)

    Google Scholar 

  28. Peyer, S.: Elmore-Delay-optimale Steinerbäume im VLSI-Design. Diploma’s Thesis (in german), Research Institute for Discrete Mathematics, University of Bonn (2000)

  29. Peyer, S., Zachariasen, M., Jørgensen, D.G.: Delay-related secondary objectives for rectilinear Steiner minimum trees. Discrete Appl. Math. 136, 271–298 (2004)

    Article  MathSciNet  MATH  Google Scholar 

  30. Rao, S., Sadayappan, P., Hwang, F., Shor, P.: The rectilinear Steiner arborescence problem. Algorithmica 7, 277–288 (1992)

    Article  MathSciNet  MATH  Google Scholar 

  31. Rao, S.B., Smith, W.D.: Approximating geometrical graphs via “spanners” and “banyans”. In: Proceedings of the Thirtieth Annual ACM Symposium on Theory of Computing, pp. 540–550. ACM, New York (1998)

  32. Rubinstein, J., Penfield, P., Horowitz, M.A.: Signal delay in RC tree networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2, 202–211 (1983)

    Article  Google Scholar 

  33. Scheifele, R.: Steiner Trees with Bounded Elmore Delay. Master’s Thesis, Research Institute for Discrete Mathematics, University of Bonn (2013)

  34. Shi, W., Su, C.: The rectilinear Steiner arborescence problem is NP-complete. SIAM J. Comput. 35, 729–740 (2005)

    Article  MathSciNet  MATH  Google Scholar 

  35. Vittal, A., Marek-Sadowska, M.: Minimal delay interconnect design using alphabetic trees. In: Proceedings of the 31st Annual Design Automation Conference, pp. 392–396. ACM (1994)

  36. Vygen, J.: Faster algorithm for optimum Steiner trees. Inf. Process. Lett. 111, 1075–1079 (2011)

    Article  MathSciNet  MATH  Google Scholar 

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Acknowledgments

We would like to thank Jens Vygen for his helpful comments and support.

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Correspondence to Rudolf Scheifele.

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Scheifele, R. Steiner Trees with Bounded RC-Delay. Algorithmica 78, 86–109 (2017). https://doi.org/10.1007/s00453-016-0149-4

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