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Electrical Engineering

, Volume 100, Issue 2, pp 519–531 | Cite as

Logic circuits dynamic parameters analysis methodology

  • Nicolae Galupa
Original Paper

Abstract

This paper presents a compact and simple procedure applicable to combinational logic circuits for timing analysis. We follow established guidelines but shall define new variables (time-dependent logic variables—TDLVs) that will improve the efficiency of the previously mentioned procedures. By using the methodology suggested we shall substitute a very laborious technique (pure delay circuit \(+\) time constant method) with a simpler procedure that will pinpoint the specific conditions for the logic circuit’s anomalous behaviour, within a few steps. The conclusion can be drawn that only a strictly limited number of situations should be considered—in conjunction with the function that is being implemented by the circuit analysed.

Keywords

Combinational logic circuits Digital hazard Primary and secondary input vector Time-dependent logic variables 

References

  1. 1.
    Beister J (1974) A unified approach to combinational hazards. IEEE Trans Comput C–23:566–575. doi: 10.1109/T-C.1974.223996 MathSciNetCrossRefzbMATHGoogle Scholar
  2. 2.
    McCluskey EJ (1986) Logic design principles. Prentice-Hall, Englewood CliffsGoogle Scholar
  3. 3.
    Tinder RF (2001) Engineering digital design, 2nd edn. Elsevier - Academic PressGoogle Scholar
  4. 4.
    Bryant R (1986) Graph-based algorithms for boolean function manipulation. IEEE Trans Comput 100(8):677–691. doi: 10.1109/TC.1986.1676819 CrossRefzbMATHGoogle Scholar
  5. 5.
    Akers S (1978) Binary decision diagrams. IEEE Trans Comput C–27:509–516. doi: 10.1109/TC.1978.1675141
  6. 6.
    Nowick SM, O’Donnell CW (2003) On the existence of hazard-free multi-level logic. In: Proceedings/IEEE ASYNC 03, May 12–16, 2003. doi: 10.1109/ASYNC.2003.1199171
  7. 7.
    Jeong C, Nowick SM (2004) Fast hazard detection in combinational circuits. ACM DAC 04:7–11. doi: 10.1109/DAC.2004.240453 Google Scholar
  8. 8.
    Berthomieu B, Diaz M (1991) Modeling and verification of time dependent systems using time petri nets. IEEE Trans Softw Eng 17:259–273. doi: 10.1109/32.75415 MathSciNetCrossRefGoogle Scholar
  9. 9.
    Brzozowski J, Seger CJH (1991) Advances in asynchronous circuit theory. Part II: bounded inertial delay model, MOS circuits, design techniques. EATCS Bull 43:199–263zbMATHGoogle Scholar
  10. 10.
    Brzozowski J, Li B, Ye Y (2010) On the complexity of the evaluation of transient extensions of boolean functions. In: 12th international workshop on descriptional complexity of formal systems, DCFS 2010Google Scholar
  11. 11.
    Maler O, Pnueli A ((1995)) Timing analysis of asynchronous circuits using timed automata. In: Correct hardware design and verification methods, 987, pp 189–205. doi: 10.1007/3-540-60385-9_12
  12. 12.
    Martello AR, Levitan SP (1993) Temporal analysis of time bounded digital systems. In: Correct hardware design and verification methods, 683, pp 27–38. doi: 10.1007/BFb0021712
  13. 13.
    Lam WKC, Brayton RK (1994) Timed boolean functions: a unified formalism for exact timing analysis. Kluwer, Dordrecht ISBN 0-7923-9454-2CrossRefzbMATHGoogle Scholar
  14. 14.
    Galupa N Increase of sequential systems performance using digital hazard analysis. In: ICCS/ISITA ’92, pp 1096–1100. ISBN: 0-7803-0803-4. doi: 10.1109/ICCS.1992.255092
  15. 15.
    Galupa N (2008) Time/logic variables used for digital hazard search. In: Proceedings of IEEE CCECE. doi: 10.1109/CCECE.2008.4564553
  16. 16.
    Stevens KS, Ginosar R, Rotem S (2002) Relative timing [asynchronous design]. In: IEEE transactions on VLSI systems, pp 129–140, ISSN 1063-8210. doi: 10.1109/TVLSI.2002.801606
  17. 17.
    Salah RB, Bozga M, Maler O (2003) On timing analysis of combinational circuits. In: FORMATS’03, LNCS 2791. Springer, Berlin, pp 204–219Google Scholar
  18. 18.
    Salah RB, Bozga M, Maler O (2007) On timed components and their abstraction. In: SAVCBS’07 workshop, ACM ISBN:978-1-59593-721-6/07/0009Google Scholar
  19. 19.
    Riedel MD, Bruck J (2014) Timing analysis of cyclic combinational circuits, Technical Report, Parallel and Distributed Systems Group, Caltech PARADISE:2004.ETR060Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2017

Authors and Affiliations

  1. 1.Technical University IasiIasiRomania

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