Linearizability on hardware weak memory models


Linearizability is a widely accepted notion of correctness for concurrent objects. Recent research has investigated redefining linearizability for particular hardware weak memory models, in particular for TSO. In this paper, we provide an overview of this research and show that such redefinitions of linearizability are not required: under an interpretation of specification behaviour which abstracts from weak memory effects, the standard definition of linearizability is sound and complete on all hardware weak memory models.We prove our result with respect to a definition of object refinement which takes a weak memory model as a parameter. The main consequence of our findings is that we can leverage the range of existing techniques and tools for standard linearizability when verifying concurrent objects running on hardware weak memory models.

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The authors would like to thank Lindsay Groves and the anonymous reviewers of this paper for their valuable feedback and advice. This work was supported by Australian Research Council Discovery Grant DP160102457.

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Correspondence to Graeme Smith.

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Smith, G., Winter, K. & Colvin, R.J. Linearizability on hardware weak memory models. Form Asp Comp 32, 1–32 (2020).

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  • Linearizability
  • Correctness
  • Concurrent objects