CNFET-Based Ultra-Low-Power Dual-\(V_{DD}\) Ternary Half Adder


This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual-\(V_{DD}\) ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (\(V_{DD}\) & \(V_{DD}/2\)) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual-\(V_{DD}\) HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (66–90% lower) than the power required by other ternary HA designs, and also exhibits 69–91% lower delays. The overall PDP of the proposed HA circuit is merely 4–11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Data Availability Statement

All the data related to the research are included in the article. Any additional data required by any reader will be provided on request to the corresponding author.


  1. 1.

    N.H. Bastani, M.H. Moaiyeri, K. Navi, Circuits. Syst. Signal Process. 37(5), 1863 (2018)

  2. 2.

    J. Deng, H.P. Wong, IEEE Trans. Electron. Devices 54(12), 3186 (2007).

  3. 3.

    J. Deng, H.P. Wong, EIEEE Trans. Electron. Devices 54, 3195 (2007)

    Article  Google Scholar 

  4. 4.

    A. Doostaregan, A. Abrishamifar, Circuits Syst. Signal Process. (2020).

  5. 5.

    O. Hashemipour, M.H. Moaiyeri, R.F. Mirzaee, A. Doostaregan, K. Navi, IET Comput. Digit. Tech. 7(4), 167 (2013)

  6. 6.

    ITRS. International Technology Roadmap for Semiconductors. (2005)

  7. 7.

    Y. Kang, J. Kim, S. Kim, S. Shin, E. Jang, J.W. Jeong, K.R. Kim, S. Kang, in 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), pp. 25–30 (2017).

  8. 8.

    S. Karmakar, J.A. Chandy, F.C. Jain, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(5), 793 (2013).

  9. 9.

    P. Keshavarzian, R. Sarikhani, Circuits. Syst. Signal Process. 33(3), 665 (2014)

  10. 10.

    S. Kim, T. Lim, S. Kang, in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 476–481 (2018).

  11. 11.

    S. Lin, Y. Kim, F. Lombardi, IEEE Trans. Nanotechnol. 10(2), 217 (2011).

  12. 12.

    M.H. Moaiyeri, S. Sedighiani, F. Sharifi, K. Navi, Front. Inf. Technol. Electron. Eng. 17(10), 1056 (2016)

  13. 13.

    J. Mounika, K. Ramanujam, M.Z. Jahangir, in 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 1–5 (2016).

  14. 14.

    S.L. Murotiya, A. Gupta, Arab. J. Sci. Eng. 39(11), 7839 (2014)

  15. 15.

    S.K. Sahoo, G. Akhilesh, R. Sahoo, M. Muglikar, IEEE Trans. Nanotechnol. 16(3), 368 (2017).

  16. 16.

    T. Sharma, L. Kumre, Circuits. Syst. Signal Process. 38(10), 4640 (2019)

  17. 17.

    S. Shin, J.W. Jeong, E. Jang, K.R. Kim, in 2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO), pp. 13–16 (2017).

  18. 18.

    B. Srinivasu, K. Sridharan, IEEE Trans. Circuits Syst. I: Reg. Pap. 64(8), 2146 (2017).

  19. 19.

    S. Tabrizchi, N. Azimi, K. Navi, Front. Inf. Technol. Electron. Eng. 18(3), 423 (2017)

  20. 20.

    S. Vidhyadharan, R. Ramakant, A.S. Vidhyadharan, A.K. Shyam, M.P. Hirpara, S.S. Dan, in 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), pp. 401–406 (2019).

  21. 21.

    S. Vidhyadharan, R. Yadav, G. Akhilesh, V. Gupta, A. Ravi, S.S. Dan, in The Physics of Semiconductor Devices, ed. by R.K. Sharma, D. Rawal (Springer International Publishing, 2019), pp. 619–628

  22. 22.

    S. Vidhyadharan, R. Yadav, S. Hariprasad, S.S. Dan, Analog Integrated Circuits and Signal Processing (2019)

  23. 23.

    S. Vidhyadharan, R. Yadav, S. Hariprasad, S.S. Dan, Springer Analog Integrated Circuits & Signal Processing (2019).

  24. 24.

    C.K. Vudadha, M. Srinivas, in 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), pp. 192–197 (2018). ISSN: 2378-2226

  25. 25.

    C. Vudadha, A. Surya, S. Agrawal, M.B. Srinivas, IEEE Trans. Circuits Syst. I: Reg. Pap. 65(12), 4313 (2018)

    Article  Google Scholar 

Download references

Author information



Corresponding author

Correspondence to Sanjay Vidhyadharan.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Vidhyadharan, A.S., Bha, K. & Vidhyadharan, S. CNFET-Based Ultra-Low-Power Dual-\(V_{DD}\) Ternary Half Adder. Circuits Syst Signal Process (2021).

Download citation


  • Ternary logic
  • Half adder
  • 45 nm CMOS technology