# Insertion of an Optimal Number of Repeaters in Pipelined Nano-interconnects for Transient Delay Minimization

## Abstract

A novel and highly accurate finite-difference time-domain model is developed for bundled single-walled carbon nanotube (SWCNT) interconnects by considering a fixed configuration that consists of a CMOS driver, a bundled SWCNT interconnect system, and an optimal number of repeaters. Using superposition theorem, this iterative model is applied to the entire chain of repeaters to calculate the total closed-loop delay. An accurate transfer function is modeled for the chain of equi-spaced repeaters in the interconnect system. The transfer function is further used to develop an analytical model for closed-loop delay, considering the optimum number of repeaters as dependent parameter. Further, in order to determine the minimum delay, an analysis is performed to find out the optimum number of repeaters for a given interconnect length. In addition, a detailed study is carried out to observe the impact of interconnect length on time delay, the time delay reduction on increasing the number of repeaters and the effect of excitation magnitude on time delay with power delay product. It is observed that by using SWCNT interconnects, the total number of repeaters and the time delay are reduced by more than 40 and 50%, respectively, compared with the copper (Cu) interconnects. However, the proposed model achieves extreme accuracy, with 4% relative tolerance at maximum, in predicting interconnect performance based on comparison with the HSPICE simulations.

## Keywords

Single-walled carbon nanotube (SWCNT) Finite-difference time domain (FDTD) Repeaters Copper (Cu) Interconnects## 1 Introduction

Interconnects play an important role in the shrinking of devices by technology, because the reduced device size signifies the lower transit time delay. As a result, the total chip performance depends on the interconnect performance [3]. Currently, far-end time delay is one of the key criteria in design considerations; hence, it is required to reduce the overall time delays at intermediate stages. Therefore, repeater insertion in intermediate stages is the best choice to avoid time delays, which cause malfunctions and logical failures [11, 16, 19]. In microelectronic circuits, copper (Cu) has a very high conductivity at room temperature [13]. At radio frequency (RF), the losses occurring in Cu conductor are governed by skin effect and its finite conductivity. When compared with Cu, the SWCNTs have higher mean free path, conductivity, ampacity and temperature-withstanding capability [14]. At radio frequency, current will flow within certain skin depth of the conductor surface, and it is dependent on the signal frequency [14, 18]. As the thickness of the conductor increases to several times the skin depth, the losses in the metal cannot be reduced effectively. Hence, the effect of frequency-dependent skin depth of the conductor decides the signal transmission from near to far end. Generally, a single SWCNT possesses a higher quantum resistance and, hence, is not suitable for interconnect applications. Therefore, a bundle of SWCNTs is preferred for high-speed interconnect applications [14, 21]. A bundled SWCNT can achieve better performance than Cu interconnects in current IC technology [6, 14, 18].

Previously, the performance analysis of interconnect lines was carried out by considering the interconnect lines as electromagnetic wave functions [15]. The best approach to solve these multivariable functions is finite-difference time-domain (FDTD) technique, which is a fast and accurate modeling algorithm [20, 24]. For high-speed interconnects, the FDTD technique is very adaptable to work with [2, 8] and easy to discretize both in time and space. Stability is an important issue in the modeling of FDTD to couple interconnects. The time step size (Δ*t*) is limited due to the Courant–Friedrichs–Lewy (CFL) stability criteria [12, 22]. Therefore, it is required to remove the time step size limitations on stability, which can be accomplished by unconditionally stable FDTD algorithm [1, 12].

In copper and multi-walled carbon nanotube (MWCNT) interconnects, repeaters are used at intermediate and global level to reduce time delays [5, 7, 17, 23]. The time delay dependency on the interconnect length is linearly monotonic while considering the inductance effect. In [16], equi-space repeaters are placed in nano- and copper interconnects to reduce time delays. In this paper, the optimal number of repeaters is obtained accurately and inserted in bundled SWCNT interconnects to reduce time delays, and the repeaters are assumed to be practical nonlinear CMOS inverters.

The rest of the paper is organized as follows: The development of a highly accurate transient time FDTD algorithm and an analytical model for delay time and optimum number of repeaters are presented in Sect. 2. Furthermore, the effect of repeater insertion on time delays along the interconnect line and a comparative study on the FDTD and empirical models are presented in Sect. 3. Finally, Sect. 4 draws a brief summary of this paper.

## 2 Modeling of Transient Time FDTD Model and Insertion of the Optimum Number of Repeaters for Time Delay Minimization

In this section, we developed an analytical model for SWCNT interconnect using frequency-dependent conductivity, and it is incorporated in FDTD model to obtain the time delay at each repeater stage. Moreover, a superposition model is used to calculate total time delay at the far end of the interconnect. Therefore, a closed-loop empirical transfer function is developed to obtain the total time delay and optimum number of repeaters required to minimize the total delay.

### 2.1 Transient Time FDTD Model for SWCNT Interconnect Line

*V*(

*z, t*) and

*I*(

*z, t*) are the voltage and current variable matrices of order {

*m*× 1} of the interconnect line, respectively, and the same variables in the Laplacian domain are represented as

*V*(

*z, s*)

*, I*(

*z, s*).

*L*and

*C*are parasitic inductance and capacitance, respectively.

*Z*(

*t*) is the total complex skin impedance of the interconnect line, and (

*z, t*) are space and time coordinates of interconnect lines.

*σ*(

*s*)) is presented in Eq. (3a).

*τ*is the momentum relaxation time;

*n*is the carrier density of CNT;

*m*

_{ q }* is the effective mass of charges;

*ω*is the angular frequency; and

*σ*

_{dc}is the dc conductivity for

*ω*= 0. The Drude model of frequency-dependent electrical conductivity is described as follows:

*ρ*(

*s*) in Eq. (4);

*h, λ*and

*q*are the Planck’s constant, the electron mean free path and the charge of carriers, respectively. Therefore, the Fermi velocity can be represented as

*υ*

_{ f }=

*λ*/

*τ*;

*R*

_{s}and

*L*

_{k}represent the scattering resistance and kinetic inductance per unit length, respectively, and

*l*is the length of the interconnect line.

*R*

_{cnt}is the combination of per-unit-length scattering resistance and a fixed quantum resistance. Therefore, the net impedance of a nanotube is expressed as

*Z*(

*s*), using Eqs. (3a) and (4), as shown in Eq. (5).

*R*

_{cnti}is the line resistance of the

*i*th line;

*C*

_{ i }is the

*i*th line capacitance;

*L*

_{ i }+

*L*

_{k}is the

*i*th line inductance; and

*M*

_{12}and

*C*

_{12}are the mutual inductance and capacitance due to flux linkage, as shown in Fig. 1. Figure 1 is an equivalent RLC model of coupled interconnect lines with CMOS repeaters. In the diagram,

*V*

_{ g }is the input voltage of CMOS;

*C*

_{dd}is the drain diffusion capacitance of CMOS;

*C*

_{Ld}is the load capacitance connected to each interconnect line; and

*R*

_{ct}is the contact resistance, due to a small imperfection between the nanotube and metal wires. The effect of contact resistance is included in the proposed model. The line inductance and resistance vary with frequency, and the line capacitive susceptance and mutual inductance also vary with input signal frequency.

For a stable FDTD technique, write the derivatives as finite forward difference, as shown in Eq. (6c), and backward difference, as shown in Eq. (2a). Equations (6c) and (2a) become (7a) and (7b), respectively.

*N*

_{ z }+ 1,

*N*

_{ z }+ 1,

*n*= 2 and

*n*=

*N*

_{ z }+ 2; the space segment Δ

*z*is replaced by Δ

*z/*2, because on the interconnect line, the distance between the current at adjacent nodes is Δ

*z/*2, as shown in Fig. 2. In Fig. 2, we show that the SWCNT interconnect line is divided into

*N*

_{ z }sections and is connected to the CMOS driver and load through the contact resistance (

*R*

_{ct}). In Fig. 2, CMOS repeater is used as load and is represented as equivalent capacitor (

*C*

_{Ld}).

*n*= 2 and

*n*=

*N*

_{ z }+ 2,

*n*= 2 and n =

*N*

_{ z }+ 2 of the near and far ends of the interconnect line as shown in Fig. 2,

*I*

_{pc}and

*I*

_{nc}are drain currents of PMOS and NMOS, respectively, in the CMOS driver, and their

*n*th power law model is reported in [12].

*C*

_{gd}is the coupling capacitance of gate to drain;

*C*

_{dd}is the drain diffusion capacitance, and the values of

*g*

_{1}and

*g*

_{2}depend on different regions of operations of the CMOS inverter [12].

*C*

_{gd}and

*C*

_{dd}matrices are required to analyze the parasitic effect of CMOS on the performance of driver interconnect load (DIL) system. Our approach is for

*m*coupled lines, if

*m*coupled lines are present, each coupled line having the

*C*

_{gd}and

*C*

_{dd}. Hence, to represent all

*m*coupled lines, the

*C*

_{gd}and

*C*

_{dd}are presented in the matrix form.

*V*,

*I*

_{ g },

*V*

_{ i }are of order

*m*(

*N*

_{ z }+ 3) × 1;

*U*is

*m*(

*N*

_{ z }+ 3) ×

*m*(

*N*

_{ z }+ 2);

*I*is

*m*(

*N*

_{ z }+ 2) × 1;

*N*is

*m*(

*N*

_{ z }+ 3) ×

*m*(

*N*

_{ z }+ 3);

*C*

_{ i }is

*m*(

*N*

_{ z }+ 3) ×

*m*(

*N*

_{ z }+ 3);

*X*is

*m*(

*N*

_{ z }+ 2) ×

*m*(

*N*

_{ z }+ 3);

*u*is identity matrix of order 2; and

*R*′,

*L*′ are

*m*(

*N*

_{ z }+ 2) ×

*m*(

*N*

_{ z }+ 2).

*η*is the number of such repeaters at intermediate stage, the proposed algorithm is applied iteratively considering one repeater at a time. The respective output delays are the inputs to Eq. (17b). Finally, by superposition theorem, the total 50% delay is the sum of the delays obtained at the output of each repeater.

*t*

_{d_repi}is the delay at the output of the

*i*th repeater, and the FDTD algorithm is applied at the output of the (

*i*− 1)th repeater via the interconnect segment to the

*i*th repeater.

### 2.2 Development of Empirical Model for Total Time Delay and Optimum Number of Repeaters

*ω*

_{n}and damping factor ξ. Hence, we can represent the combined form as a transfer function, as shown in Eq. (18).

*t*

_{delay}is the time taken for the response to reach 50% of its final steady-state value. For SWCNT interconnect, the transfer function models the expression for the 50% delay time, which includes interconnect parasitics and driver small-signal equivalents, as shown in Eq. (20):

*C*

_{d0},

*C*

_{ gi }and

*r*

_{d0}are the small-signal output capacitance (~ 0.032fF), input capacitance (~ 0.07fF) and output resistance (50 KΩ) of the minimum-sized gate in the interconnect line, respectively.

*θ*is the ratio of driver or load size to minimum gate size.

*η*

_{opt}is the optimum number of repeaters required to achieve the minimum delay. From [16], we develop a formula for configuring the parasitics shown in Fig. 1. The line resistance (

*R*

_{cnt}) and contact resistance (

*R*

_{ct}) occur due to a small imperfection between the nanotube and metal wires.

*l*and

*r*

_{d0}are the length of the interconnect and internal resistance of the repeater, respectively.

*C*

_{d0}and

*C*

_{ gi }are the small-signal capacitances of the CMOS repeater used in Eq. (25).

*η*

_{opt}is the optimum number of repeaters. In this work, the size of all CMOS repeaters is considered as equal, and the fitting parameter

*β*has a unique value of 0.25 for SWCNT interconnect.

## 3 Results and Discussion

This section analyzes the delay of the SWCNT interconnect with respect to the optimum number of repeaters and interconnect length. The dependency of the optimum number of repeaters on interconnect length is observed with conventional copper (Cu) interconnects. The FDTD and empirical simulations are carried out using MATLAB, and the validations for different cases are done using HSPICE.

### 3.1 Delay Time Variation with Respect to Interconnect Length Without Repeaters

Comparison of delays between Cu and SWCNT interconnect with respect to interconnect length

Interconnect length (µm) | 16-nm technology node (ns) | % Error between FDTD and HSPICE for SWCNT | 32-nm technology node (ns) | % Error between FDTD and HSPICE for SWCNT | ||||
---|---|---|---|---|---|---|---|---|

Cu (HSPICE) | SWCNT (HSPICE) | SWCNT (FDTD) | Cu (HSPICE) | SWCNT (HSPICE) | SWCNT (FDTD) | |||

10 | 3.2 | 2.3 | 2.24 | 2.6 | 2.2 | 1.5 | 1.55 | − 2.5 |

100 | 12.35 | 10.5 | 10.9 | − 3.8 | 10.6 | 8.3 | 8.45 | − 1.8 |

200 | 26.35 | 20.6 | 21 | − 1.94 | 26 | 16 | 16.34 | − 2.15 |

400 | 47.45 | 31.2 | 31.4 | − 0.6 | 42 | 24 | 24.1 | − 0.41 |

600 | 59.45 | 41.3 | 41.6 | − 0.72 | 59.45 | 35 | 35.1 | − 0.285 |

800 | 81 | 75 | 76 | − 1.3 | 82 | 62 | 61.7 | 0.48 |

1000 | 110 | 95 | 97 | − 2.1 | 97 | 82 | 82.6 | − 0.731 |

### 3.2 Selection of the Optimum Number of Repeaters Based on Interconnect Length

*l*in Eq. (18) and the repeater’s small-signal impedances will determine the optimum number of repeaters needed to obtain minimum delay. In Fig. 5a, b, simulation results are presented for copper and SWCNT interconnects, which show that the number of repeaters required for copper is more compared with SWCNT for a given interconnect length. As the technology changes from 16 to 32 nm, the number of repeaters required reduces subsequently for both copper and SWCNT interconnects. The number of repeaters required is increased monotonically as a function of interconnect length, as shown in Table 2. If SWCNT interconnects are used instead of copper interconnects, the number of repeaters required is compressed by more than 40%.

Number of repeaters required based on interconnect length and technology node

Interconnect length in (µm) | Optimum repeaters ( (16-nm technology node) | Interconnect length in (µm) | Optimum repeaters ( (32-nm technology node) | ||
---|---|---|---|---|---|

Copper (Cu) | SWCNT | Copper (Cu) | SWCNT | ||

10 | 1 | 1 | 500 | 2 | 1 |

100 | 5 | 2 | 1000 | 3 | 1 |

200 | 8 | 2 | 1500 | 4 | 2 |

300 | 9 | 3 | 2000 | 4 | 2 |

400 | 11 | 3 | 2500 | 5 | 2 |

500 | 12 | 3 | 3000 | 5 | 3 |

600 | 13 | 4 | 3500 | 6 | 3 |

700 | 15 | 4 | 4000 | 6 | 3 |

800 | 16 | 4 | 4500 | 7 | 3 |

900 | 17 | 5 | 5000 | 8 | 4 |

1000 | 18 | 5 | – | – | – |

### 3.3 Interconnect Delay Analysis with Respect to Repeaters

Comparison of delays between Cu and SWCNT interconnects with respect to the number of repeaters and error using the proposed FDTD

Number of repeaters used ( | Time delay (ns) (16-nm technology node) | % Error between FDTD and HSPICE for SWCNT | Time delay (ns) (32-nm technology node) | % Error between FDTD and HSPICE for SWCNT | ||||
---|---|---|---|---|---|---|---|---|

Cu (HSPICE) | SWCNT (HSPICE) | SWCNT (FDTD) | Cu (HSPICE) | SWCNT (HSPICE) | SWCNT (FDTD) | |||

2 | 9.3 | 3.34 | 3.4 | − 1.8 | 10.4 | 3.62 | 3.69 | − 1.93 |

4 | 6.3 | 2.305 | 2.38 | − 3.25 | 7.3 | 2.78 | 2.81 | − 1.08 |

6 | 4.32 | 1.89 | 1.91 | − 1.06 | 6.1 | 2.21 | 2.25 | − 1.81 |

8 | 3.18 | 1.663 | 1.7 | − 2.22 | 4.2 | 1.83 | 1.91 | − 4.37 |

10 | 2.43 | 1.544 | 1.53 | 0.91 | 3.2 | 1.62 | 1.69 | − 4.3 |

*η*= 2, 4, 6, 8 and 10, and the delay time at the far end is decreased accordingly, as depicted in Fig. 8. In Fig. 9, for

*η*= 10 repeaters, the response at the output of each repeater along the interconnect line is depicted, and these responses are used to estimate the delay times, as shown in Eq. (17b). The effect of voltage excitation on time delay is reported in Table 4. As the magnitude of excitation increases, the delay time is reduced monotonically for a given number of repeaters. The power delay product is also reduced for minimum voltage magnitude and is based on the square-law proportionality between power and excitation magnitude, as reported in Table 4.

Delay time variation with respect to voltage and repeater variations

Number of repeaters ( | Delay for different supply voltages (ns) | ||||||
---|---|---|---|---|---|---|---|

0.8 V | 0.75 V | 0.7 V | 0.65 V | 0.6 V | 0.55 V | 0.5 V | |

2 | 3.322 | 3.334 | 3.348 | 3.379 | 3.442 | 3.558 | 3.778 |

4 | 2.269 | 2.283 | 2.305 | 2.343 | 2.413 | 2.532 | 2.746 |

6 | 1.857 | 1.869 | 1.890 | 1.972 | 1.991 | 2.103 | 2.295 |

8 | 1.629 | 1.640 | 1.663 | 1.698 | 1.757 | 1.860 | 2.041 |

10 | 1.558 | 1.573 | 1.594 | 1.631 | 1.694 | 1.798 | 1.979 |

Power delay product | 0.335 | 0.208 | 0.124 | 0.072 | 0.043 | 0.026 | 0.018 |

Figures 8 and 9 are the output waveforms of SWCNT interconnect-based system with CMOS driver, repeaters and load. We inserted 10 CMOS repeaters in SWCNT-based interconnect line and applied logic 1 (0–0.7 V) as input to the CMOS driver and observed logic 0 (0.7–0 V) as output for each even number of repeaters (2, 4, 6, 8 and 10) at the intermediate stage of SWCNT interconnect line. In Fig. 8, we plotted the output for each stage of even number of repeaters and observed the reduction in signal delay. Similarly, in Fig. 9, we also plotted the output of each single repeater in an interconnect line and observed the effect of repeaters on signal delay. The signal time delays are noted and shown in Table 3, by varying the number of repeaters for Cu and SWCNT interconnect line.

## 4 Conclusion

The proposed highly accurate transient time FDTD model satisfied an extreme accuracy limit of 97% to the predicted delay time at the far end of the interconnect and is validated by inserting the optimal number of repeaters and no repeaters in the intermediate stage. It is also proved that a longer interconnect length is the cause of delay in the transient period, and the best solution to this is to incorporate the optimum number of repeaters in it. The responses obtained using FDTD is the same compared with empirical formula and HSPICE simulations. Further, it is demonstrated that the optimum number of repeaters required for SWCNT interconnects is reduced by more than 40% compared with copper interconnects, and the repeater insertion improves transient performance in terms of delay time.

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