Advertisement

Insertion of an Optimal Number of Repeaters in Pipelined Nano-interconnects for Transient Delay Minimization

  • C. Venkataiah
  • K. Satyaprasad
  • T. Jayachandra Prasad
Article

Abstract

A novel and highly accurate finite-difference time-domain model is developed for bundled single-walled carbon nanotube (SWCNT) interconnects by considering a fixed configuration that consists of a CMOS driver, a bundled SWCNT interconnect system, and an optimal number of repeaters. Using superposition theorem, this iterative model is applied to the entire chain of repeaters to calculate the total closed-loop delay. An accurate transfer function is modeled for the chain of equi-spaced repeaters in the interconnect system. The transfer function is further used to develop an analytical model for closed-loop delay, considering the optimum number of repeaters as dependent parameter. Further, in order to determine the minimum delay, an analysis is performed to find out the optimum number of repeaters for a given interconnect length. In addition, a detailed study is carried out to observe the impact of interconnect length on time delay, the time delay reduction on increasing the number of repeaters and the effect of excitation magnitude on time delay with power delay product. It is observed that by using SWCNT interconnects, the total number of repeaters and the time delay are reduced by more than 40 and 50%, respectively, compared with the copper (Cu) interconnects. However, the proposed model achieves extreme accuracy, with 4% relative tolerance at maximum, in predicting interconnect performance based on comparison with the HSPICE simulations.

Keywords

Single-walled carbon nanotube (SWCNT) Finite-difference time domain (FDTD) Repeaters Copper (Cu) Interconnects 

1 Introduction

Interconnects play an important role in the shrinking of devices by technology, because the reduced device size signifies the lower transit time delay. As a result, the total chip performance depends on the interconnect performance [3]. Currently, far-end time delay is one of the key criteria in design considerations; hence, it is required to reduce the overall time delays at intermediate stages. Therefore, repeater insertion in intermediate stages is the best choice to avoid time delays, which cause malfunctions and logical failures [11, 16, 19]. In microelectronic circuits, copper (Cu) has a very high conductivity at room temperature [13]. At radio frequency (RF), the losses occurring in Cu conductor are governed by skin effect and its finite conductivity. When compared with Cu, the SWCNTs have higher mean free path, conductivity, ampacity and temperature-withstanding capability [14]. At radio frequency, current will flow within certain skin depth of the conductor surface, and it is dependent on the signal frequency [14, 18]. As the thickness of the conductor increases to several times the skin depth, the losses in the metal cannot be reduced effectively. Hence, the effect of frequency-dependent skin depth of the conductor decides the signal transmission from near to far end. Generally, a single SWCNT possesses a higher quantum resistance and, hence, is not suitable for interconnect applications. Therefore, a bundle of SWCNTs is preferred for high-speed interconnect applications [14, 21]. A bundled SWCNT can achieve better performance than Cu interconnects in current IC technology [6, 14, 18].

Previously, the performance analysis of interconnect lines was carried out by considering the interconnect lines as electromagnetic wave functions [15]. The best approach to solve these multivariable functions is finite-difference time-domain (FDTD) technique, which is a fast and accurate modeling algorithm [20, 24]. For high-speed interconnects, the FDTD technique is very adaptable to work with [2, 8] and easy to discretize both in time and space. Stability is an important issue in the modeling of FDTD to couple interconnects. The time step size (Δt) is limited due to the Courant–Friedrichs–Lewy (CFL) stability criteria [12, 22]. Therefore, it is required to remove the time step size limitations on stability, which can be accomplished by unconditionally stable FDTD algorithm [1, 12].

In copper and multi-walled carbon nanotube (MWCNT) interconnects, repeaters are used at intermediate and global level to reduce time delays [5, 7, 17, 23]. The time delay dependency on the interconnect length is linearly monotonic while considering the inductance effect. In [16], equi-space repeaters are placed in nano- and copper interconnects to reduce time delays. In this paper, the optimal number of repeaters is obtained accurately and inserted in bundled SWCNT interconnects to reduce time delays, and the repeaters are assumed to be practical nonlinear CMOS inverters.

The rest of the paper is organized as follows: The development of a highly accurate transient time FDTD algorithm and an analytical model for delay time and optimum number of repeaters are presented in Sect. 2. Furthermore, the effect of repeater insertion on time delays along the interconnect line and a comparative study on the FDTD and empirical models are presented in Sect. 3. Finally, Sect. 4 draws a brief summary of this paper.

2 Modeling of Transient Time FDTD Model and Insertion of the Optimum Number of Repeaters for Time Delay Minimization

In this section, we developed an analytical model for SWCNT interconnect using frequency-dependent conductivity, and it is incorporated in FDTD model to obtain the time delay at each repeater stage. Moreover, a superposition model is used to calculate total time delay at the far end of the interconnect. Therefore, a closed-loop empirical transfer function is developed to obtain the total time delay and optimum number of repeaters required to minimize the total delay.

2.1 Transient Time FDTD Model for SWCNT Interconnect Line

Generally, transmission line model is best suited to analyze coupled interconnect lines, as both have similar RLC distributed elements [2, 15]. The transmission line expressions for two coupled lines with Laplacian parasitics are modeled in Eqs. (1a) and (2a), and their frequency-domain representations are shown in Eqs. (1b) and (2b).
$$ \frac{\partial V(z,t)}{\partial z} + L\frac{\partial I(z,t)}{\partial t} + Z(t)\,I(z,t) = 0\, $$
(1a)
$$ \frac{\partial V(z,s)}{\partial z} + sLI(z,s) + Z(s)\,I(z,s) = 0\, $$
(1b)
$$ C\frac{\partial V(z,t)}{\partial t} = - \frac{\partial I(z,t)}{\partial z}\,\, $$
(2a)
$$ CsV(z,s) + \frac{\partial I(z,s)}{\partial z} = 0\,\,, $$
(2b)
where V(z, t) and I(z, t) are the voltage and current variable matrices of order {m × 1} of the interconnect line, respectively, and the same variables in the Laplacian domain are represented as V(z, s), I(z, s). L and C are parasitic inductance and capacitance, respectively. Z(t) is the total complex skin impedance of the interconnect line, and (z, t) are space and time coordinates of interconnect lines.
A Drude model [4] for complex conductivity of metallic SWCNT interconnect (σ(s)) is presented in Eq. (3a). τ is the momentum relaxation time; n is the carrier density of CNT; m q * is the effective mass of charges; ω is the angular frequency; and σdc is the dc conductivity for ω = 0. The Drude model of frequency-dependent electrical conductivity is described as follows:
$$ \sigma (s) = \frac{{\sigma_{\text{dc}} }}{1 + s\tau } $$
(3a)
$$ \sigma_{\text{dc}} = \sigma_{s \to 0} = \frac{{nq^{2} \tau }}{{m_{q}^{*} }}. $$
(3b)
Using Eq. (3a), the complex resistivity is represented as ρ(s) in Eq. (4); h, λ and q are the Planck’s constant, the electron mean free path and the charge of carriers, respectively. Therefore, the Fermi velocity can be represented as υ f  = λ/τ; Rs and Lk represent the scattering resistance and kinetic inductance per unit length, respectively, and l is the length of the interconnect line.
$$ \rho (s) = \frac{h}{{2q^{2} \lambda }}(1 + s\tau ) = R_{\text{s}} + sL_{\text{k}} . $$
(4)
Practically, the total resistance of a nanotube Rcnt is the combination of per-unit-length scattering resistance and a fixed quantum resistance. Therefore, the net impedance of a nanotube is expressed as Z(s), using Eqs. (3a) and (4), as shown in Eq. (5).
$$ Z(s) = \frac{h}{{4q^{2} }}\left( {1 + \frac{l}{\lambda }} \right) + s\left( {\frac{hl}{{8q^{2} \upsilon_{f} }}} \right) = R_{\text{cnt}} + sL_{\text{k}} . $$
(5)
On substituting Eq. (5) in Eq. (1b), we get Eq. (6a). Conversion to time domain using inverse transform yields Eqs. (6b) and (6c).
$$ \frac{\partial V(z,s)}{\partial z} + sLI(z,s) + \frac{h}{{4q^{2} }}\left( {1 + \frac{l}{\lambda }} \right)I(z,s) + s\left( {\frac{hl}{{8q^{2} \upsilon_{f} }}} \right)I(z,s) = 0\, $$
(6a)
$$ \frac{\partial V(z,t)}{\partial z} + L\frac{\partial I(z,t)}{\partial t} + \frac{h}{{4q^{2} }}\left( {1 + \frac{l}{\lambda }} \right)\delta (t)*I(z,t) + \left( {\frac{hl}{{8q^{2} \upsilon_{f} }}} \right)\frac{\partial }{\partial t}(\delta (t)*I(z,t)) = 0\, $$
(6b)
$$ \frac{\partial V(z,t)}{\partial z} + \left( {L + \left( {\frac{hl}{{8q^{2} \upsilon_{f} }}} \right)} \right)\frac{\partial I(z,t)}{\partial t} + \frac{h}{{4q^{2} }}\left( {1 + \frac{l}{\lambda }} \right)I(z,t) = 0\, $$
(6c)
$$ \begin{aligned} R_{\text{cnt}} & = \left( {\begin{array}{*{20}c} {R_{{{\text{cnt}}1}} } & 0 \\ 0 & {R_{{{\text{cnt}}2}} } \\ \end{array} } \right)\quad C = \left( {\begin{array}{*{20}c} {C_{1} + C_{12} } & { - C_{12} } \\ { - C_{12} } & {C_{2} + C_{12} } \\ \end{array} } \right) \\ L_{\text{T}} & = L + L_{\text{k}} = \left( {\begin{array}{*{20}c} {L_{1} } & {M_{12} } \\ {M_{12} } & {L_{2} } \\ \end{array} } \right) + \left( {\begin{array}{*{20}c} {L_{{{\text{k}}1}} } & 0 \\ 0 & {L_{{{\text{k}}2}} } \\ \end{array} } \right), \\ \end{aligned} $$
where Rcnti is the line resistance of the ith line; C i is the ith line capacitance; L i + Lk is the ith line inductance; and M12 and C12 are the mutual inductance and capacitance due to flux linkage, as shown in Fig. 1. Figure 1 is an equivalent RLC model of coupled interconnect lines with CMOS repeaters. In the diagram, V g is the input voltage of CMOS; Cdd is the drain diffusion capacitance of CMOS; CLd is the load capacitance connected to each interconnect line; and Rct is the contact resistance, due to a small imperfection between the nanotube and metal wires. The effect of contact resistance is included in the proposed model. The line inductance and resistance vary with frequency, and the line capacitive susceptance and mutual inductance also vary with input signal frequency.
Fig. 1

Coupled lines equivalent RLC model with active repeaters between source and load

For a stable FDTD technique, write the derivatives as finite forward difference, as shown in Eq. (6c), and backward difference, as shown in Eq. (2a). Equations (6c) and (2a) become (7a) and (7b), respectively.

For n = 2, 3, …, N z + 1,
$$ \left( {V_{n + 1} - V_{n} } \right)/\Delta z + \frac{h}{{4q^{2} }}\left( {1 + \frac{l}{\lambda }} \right)\,I_{n} + \left( {L + \left( {\frac{hl}{{8q^{2} \upsilon_{f} }}} \right)} \right)\frac{{\partial I_{n} }}{\partial t} = 0. $$
(7a)
For n = 3, 4, 5, …, N z + 1,
$$ \left( {I_{n} - I_{n - 1} } \right)/\Delta z = - C\,\,\frac{{\partial V_{n} }}{\partial t}. $$
(7b)
In Eq. (7b), n = 2 and n = N z + 2; the space segment Δz is replaced by Δz/2, because on the interconnect line, the distance between the current at adjacent nodes is Δz/2, as shown in Fig. 2. In Fig. 2, we show that the SWCNT interconnect line is divided into N z sections and is connected to the CMOS driver and load through the contact resistance (Rct). In Fig. 2, CMOS repeater is used as load and is represented as equivalent capacitor (CLd).
Fig. 2

Space discretization of SWCNT interconnect line with CMOS driver and load repeater assumed as a capacitive load

For n = 2 and n = N z + 2,
$$ I_{2} - I_{1} = \frac{{\Delta z\,C}}{2}\,\frac{{\partial V_{2} }}{\partial t} $$
(8a)
$$ \frac{{C\,\Delta z}}{2}\frac{{\partial V_{Nz + 2} }}{\partial t} = I_{Nz + 1} - I_{Nz + 2} \,\,\,\,\,. $$
(8b)
On applying KCL at node n = 2 and n = N z + 2 of the near and far ends of the interconnect line as shown in Fig. 2,
$$ \frac{{C\,\Delta z}}{2}\frac{{\partial V_{Nz + 2} }}{\partial t} = \left[ {\frac{{V_{Nz + 3} - V_{Nz + 2} }}{{R_{\text{ct}} }}} \right] + I_{Nz + 1} \, $$
(9a)
$$ C\frac{{\partial V_{2} }}{\partial t} = \frac{2}{{\Delta z}}\left[ {\frac{{V_{1} - V_{2} }}{{R_{\text{ct}} }}} \right] - I_{2} \,\,\,\,. $$
(9b)
Now, KCL can be applied to provide a relationship between the driver and the near end of the interconnect line as shown in Eq. (10a). Later, incorporation of Eq. (8a) in Eq. (10a) reveals the final expression (10b) as follows:
$$ I_{\text{pc}} - C_{\text{dd}} \frac{{\partial V_{1} }}{\partial t} = I_{1} + I_{\text{nc}} - C_{\text{gd}} \frac{{\partial (V_{g} - V_{1} )}}{\partial t} $$
(10a)
$$ I_{\text{pc}} - C_{\text{dd}} \frac{{\partial V_{1} }}{\partial t} = \frac{{\Delta z}}{2}C\frac{{\partial V_{2} }}{\partial t} + I_{2} + I_{\text{nc}} - C_{\text{gd}} \frac{{\partial (V_{g} - V_{1} )}}{\partial t}, $$
(10b)
where Ipc and Inc are drain currents of PMOS and NMOS, respectively, in the CMOS driver, and their nth power law model is reported in [12]. Cgd is the coupling capacitance of gate to drain; Cdd is the drain diffusion capacitance, and the values of g1 and g2 depend on different regions of operations of the CMOS inverter [12]. Cgd and Cdd matrices are required to analyze the parasitic effect of CMOS on the performance of driver interconnect load (DIL) system. Our approach is for m coupled lines, if m coupled lines are present, each coupled line having the Cgd and Cdd. Hence, to represent all m coupled lines, the Cgd and Cdd are presented in the matrix form.
$$ C_{\text{gd}} = \left( {\begin{array}{*{20}c} {C_{{{\text{gd}}1}} } & 0 & 0 \\ 0 & \ddots & 0 \\ 0 & 0 & {C_{{{\text{gd}}m}} } \\ \end{array} } \right)_{{}} \quad C_{\text{dd}} = \left( {\begin{array}{*{20}c} {C_{{{\text{dd}}1}} } & 0 & 0 \\ 0 & \ddots & 0 \\ 0 & 0 & {C_{{{\text{dd}}m}} } \\ \end{array} } \right). $$
Applying KCL at the far end of interconnects results in an expression related to interconnect and load, as shown in Eq. (11).
$$ I_{Nz + 2} = C_{\text{Ld}} \frac{{\partial V_{Nz + 3} }}{\partial t}. $$
(11)
The above KCL expressions presented in Eqs. (9a), (9b), (10b) and (11) are combined to formulate state equations, as shown in Eq. (12), and Eq. (7a) in state equation form is presented in Eq. (13); their matrix representations are shown in Eqs. (14) and (15).
$$ C_{i} \frac{{\partial V_{i} }}{\partial t} - N\frac{\partial V}{\partial t} = UI + GV - i_{g} $$
(12)
$$ L^{\prime } \frac{\partial I}{\partial t} = - XV - R^{\prime } I\,\, $$
(13)
$$ \begin{aligned} & \left( {\begin{array}{*{20}r} \hfill{C_{\text{gd}} } & \hfill 0 & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \ddots & \hfill \vdots & \hfill \vdots \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 \\ \end{array} } \right)\frac{\partial }{\partial t}\left( {\begin{array}{*{20}c} {V_{g} } \\ 0 \\ \vdots \\ 0 \\ \end{array} } \right)\\ &\quad- \left( {\begin{array}{*{20}r} \hfill {C_{\text{gd}} + C_{\text{dd}} } & \hfill 0 & \hfill 0 & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill {C(\Delta z/2)} & \hfill 0 & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill {C\Delta z} & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill {C\Delta z} & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill {C(\Delta z/2)} & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill {C_{\text{Ld}} } \\ \end{array} } \right)\frac{\partial }{\partial t}\left( {\begin{array}{*{20}c} {V_{1} } \\ {V_{2} } \\ \vdots \\ {V_{Nz + 3} } \\ \end{array} } \right) \\ & \quad = \left( \begin{aligned} \begin{array}{*{20}c} u & 0 & {0 \cdots \cdots } \\ 0 & u & {0 \cdots \cdots } \\ 0 & { - u} & {u \cdots \cdots } \\ \end{array} \begin{array}{*{20}c} \cdots & 0 & {} \\ \cdots & 0 & {} \\ \cdots & 0 & {} \\ \end{array} \begin{array}{*{20}r} \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 \\ \end{array} \hfill \\ \begin{array}{*{20}c} \vdots & \vdots & \vdots \\ 0 & 0 & 0 \\ 0 & 0 & 0 \\ 0 & 0 & 0 \\ \end{array} \begin{array}{*{20}r} \hfill \ddots & \hfill \ddots & \hfill \vdots & \hfill \vdots & \hfill \vdots \\ \hfill \cdots & \hfill \cdots & \hfill { - u} & \hfill u & \hfill 0 \\ \hfill \cdots & \hfill \cdots & \hfill 0 & \hfill { - u} & \hfill 0 \\ \hfill \cdots & \hfill \cdots & \hfill 0 & \hfill 0 & \hfill { - u} \\ \end{array} \hfill \\ \end{aligned} \right)\left( {\begin{array}{*{20}c} {I_{1} } \\ {I_{2} } \\ \vdots \\ {I_{Nz + 2} } \\ \end{array} } \right) \\ &\quad+ \left( \begin{aligned} \begin{array}{*{20}c} {g_{1} } & 0 & {0 \cdots \cdots } \\ {\frac{ - 1}{{R_{\text{ct}} }}} & {\frac{1}{{R_{\text{ct}} }}} & {0 \cdots \cdots } \\ 0 & 0 & {0 \cdots \cdots } \\ \end{array} \begin{array}{*{20}r} \hfill {} & \hfill 0 & \hfill 0 & \hfill {} & \hfill 0 \\ \hfill {} & \hfill 0 & \hfill 0 & \hfill {} & \hfill 0 \\ \hfill {} & \hfill {} & \hfill {} & \hfill {} & \hfill {} \\ \hfill {} & \hfill 0 & \hfill 0 & \hfill {} & \hfill 0 \\ \end{array} \hfill \\ \begin{array}{*{20}r} \hfill \vdots & \hfill {} & \hfill \vdots & \hfill \vdots \\ \hfill 0 & \hfill {} & \hfill 0 & \hfill 0 \\ \hfill {} & \hfill {} & \hfill {} & \hfill {} \\ \hfill 0 & \hfill {} & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill {} & \hfill 0 & \hfill 0 \\ \end{array} \begin{array}{*{20}r} \hfill \ddots & \hfill \ddots & \hfill \vdots & \hfill \vdots & \hfill \vdots \\ \hfill \cdots & \hfill \cdots & \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill \cdots & \hfill \cdots & \hfill 0 & \hfill {\frac{1}{{R_{\text{ct}} }}} & \hfill {\frac{ - 1}{{R_{\text{ct}} }}} \\ \hfill \cdots & \hfill \cdots & \hfill 0 & \hfill 0 & \hfill 0 \\ \end{array} \hfill \\ \end{aligned} \right)\left( {\begin{array}{*{20}c} {V_{1} } \\ {V_{2} } \\ \vdots \\ {V_{Nz + 3} } \\ \end{array} } \right) - \left( {\begin{array}{*{20}c} {g_{2} } \\ 0 \\ \vdots \\ 0 \\ \end{array} } \right)\, \\ \end{aligned} $$
(14)
$$ \begin{aligned} & \left( {\begin{array}{*{20}r} \hfill 0 & \hfill 0 & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill {(L_{1} + L_{k1} )\Delta z} & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill {(L_{2} + L_{k2} )\Delta z} & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \ddots & \hfill \vdots & \hfill \vdots \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill {(L_{Nz + 1} + L_{Nz + 1} )\Delta z} & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 \\ \end{array} } \right)\frac{\partial }{\partial t}\left( {\begin{array}{*{20}c} {I_{1} } \\ {I_{2} } \\ \vdots \\ {I_{Nz + 2} } \\ \end{array} } \right) \\ & \quad = - \left( \begin{aligned} \begin{array}{*{20}c} 0 & 0 & 0 & 0 \\ 0 & { - u} & u & 0 \\ 0 & 0 & { - u} & u \\ \vdots & \vdots & \vdots & \vdots \\ \end{array} \begin{array}{*{20}c} \cdots & 0 & 0 & 0 \\ \cdots & 0 & 0 & 0 \\ \cdots & 0 & 0 & 0 \\ \ddots & \vdots & \vdots & \vdots \\ \end{array} \hfill \\ \begin{array}{*{20}r} \hfill 0 & \hfill 0 & \hfill {} & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill {} & \hfill 0 & \hfill 0 \\ \hfill {} & \hfill {} & \hfill {} & \hfill {} & \hfill {} \\ \end{array} \begin{array}{*{20}r} \hfill \cdots & \hfill { - u} & \hfill u & \hfill 0 & \hfill {} \\ \hfill \cdots & \hfill 0 & \hfill 0 & \hfill 0 & \hfill {} \\ \hfill {} & \hfill {} & \hfill {} & \hfill {} & \hfill {} \\ \end{array} \hfill \\ \end{aligned} \right)\left( {\begin{array}{*{20}c} {V_{1} } \\ {V_{2} } \\ \vdots \\ {V_{Nz + 3} } \\ \end{array} } \right) \\ & \quad \quad - \left( {\begin{array}{*{20}r} \hfill 0 & \hfill 0 & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill {R_{{{\text{cnt}}1}}\Delta z} & \hfill 0 & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill {R_{{{\text{cnt}}2}} \Delta z} & \hfill \cdots & \hfill 0 & \hfill 0 \\ \hfill \vdots & \hfill \vdots & \hfill \vdots & \hfill \ddots & \hfill \vdots & \hfill \vdots \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill {R_{{{\text{cnt}}Nz + 1}} \Delta z} & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 & \hfill 0 \\ \end{array} } \right)\left( {\begin{array}{*{20}c} {I_{1} } \\ {I_{2} } \\ \vdots \\ {I_{Nz + 2} } \\ \end{array} } \right), \\ \end{aligned} $$
(15)
where V, I g , V i are of order m(N z + 3) × 1; U is m(N z + 3) × m(N z + 2); I is m(N z + 2) × 1; N is m(N z + 3) × m(N z + 3); C i is m(N z + 3) × m(N z + 3); X is m(N z + 2) ×  m(N z + 3); u is identity matrix of order 2; and R′, L′ are m(N z + 2) × m(N z + 2).
Applying FDTD to Eqs. (12) and (13) results in an iterative algorithm for interconnect line voltage and currents as shown in Eqs. (16) and (17):
$$ I^{k + 1} = \left[ {\frac{{L^{{\prime }} }}{{\Delta t}} + \frac{{R^{{\prime }} }}{2}} \right]^{ - 1} \left[ { - X\left( {\frac{{V^{k + 1} + V^{k} }}{2}} \right) + I^{k} \left( {\frac{{L^{{\prime }} }}{{\Delta t}} - \frac{{R^{{\prime }} }}{2}} \right)} \right] $$
(16)
$$\begin{aligned} V^{k + 1} &= \left[ {\frac{G}{2} + \frac{N}{{\Delta t}} + \frac{UX}{4}\left( {\frac{{L^{\prime } }}{{\Delta t}} + \frac{{R^{\prime } }}{2}} \right)^{ - 1} } \right]^{ - 1} \\ & \quad \left[ \begin{aligned} C_{i} \left( {\frac{{V_{{i^{k + 1} - V_{i}^{k} }} }}{\Delta t}} \right) - I^{k} \left( {\frac{U}{2} + \frac{U}{2}\left( {\frac{{L^{\prime } }}{\Delta t} + \frac{{R^{\prime } }}{2}} \right)^{ - 1} \left( {\frac{{L^{\prime } }}{\Delta t} - \frac{{R^{\prime } }}{2}} \right)} \right) \hfill \\ + \left( {\frac{{I_{{g^{k + 1} + I_{g}^{k} }} }}{2}} \right) + V^{k} \left( { - \frac{G}{2} + \frac{N}{\Delta t} + \frac{UX}{4}\left( {\frac{{L^{\prime } }}{{\Delta t}} + \frac{{R^{\prime } }}{2}} \right)^{ - 1} } \right) \hfill \\ \end{aligned} \right]. \end{aligned}$$
(17a)
The above iterative algorithm is used to calculate the 50% time delay for one repeater in the interconnect system. If η is the number of such repeaters at intermediate stage, the proposed algorithm is applied iteratively considering one repeater at a time. The respective output delays are the inputs to Eq. (17b). Finally, by superposition theorem, the total 50% delay is the sum of the delays obtained at the output of each repeater.
$$ t_{{{\text{delay}}\_{\text{FDTD}}}} = \sum\limits_{J = 1}^{\eta } {t_{{{\text{d}}\_{\text{rep}}k}} } = t_{{{\text{d}}\_{\text{rep}}1}} + t_{{{\text{d}}\_{\text{rep}}2}} + \cdots + t_{{{\text{d}}\_{\text{rep}}i}} + \cdots + t_{{{\text{d}}\_{\text{rep}}\eta }} , $$
(17b)
where td_repi is the delay at the output of the ith repeater, and the FDTD algorithm is applied at the output of the (i − 1)th repeater via the interconnect segment to the ith repeater.

2.2 Development of Empirical Model for Total Time Delay and Optimum Number of Repeaters

The proposed model primarily consists of a CMOS driver, a SWCNT interconnect system with optimum number of repeaters and a load capacitance as shown in Fig. 3. The repeaters are assumed to be implemented as CMOS inverters. In order to accurately analyze the delay, the SWCNT interconnect should be accompanied by an optimum number of inverters. The closed-loop transfer function expression is modeled as shown in Eq. (18) for the SWCNT interconnect system. The second-order system transfer function is expressed as shown in Eq. (19). The response between the near and far ends is represented by under-damped system response. Therefore, it contains natural frequency of oscillations ωn and damping factor ξ. Hence, we can represent the combined form as a transfer function, as shown in Eq. (18).
$$ T_{\text{CL}} (s) = \frac{{1/[(L + L_{\text{k}} )l(Cl + \theta C_{gi} )]}}{{s^{2} + 2\frac{{\left( {R_{\text{cnt}} l + 2R_{\text{ct}} } \right)}}{{2(L + L_{\text{k}} )}}\sqrt {\frac{C}{{l(Cl + \theta C_{gi} )}}} \left[ {\frac{{R_{\text{t}} + C_{\text{t}} + R_{\text{t}} C_{\text{t}} \left( {1 + \frac{{C_{d 0} }}{{C_{gi} }}} \right) + 0.5}}{{\sqrt {1 + C_{\text{t}} } }}} \right]s + 1/[(L + L_{\text{k}} )l(Cl + \theta C_{\text{gi}} )]}}. $$
(18)
$$ T(s) = (\omega_{n} /s^{2} + 2\xi \omega_{n} s + \omega_{n}^{2} ). $$
(19)
The tdelay is the time taken for the response to reach 50% of its final steady-state value. For SWCNT interconnect, the transfer function models the expression for the 50% delay time, which includes interconnect parasitics and driver small-signal equivalents, as shown in Eq. (20):
$$ t_{\text{delay}} = \frac{0.74}{{\omega_{n} }}\sqrt {\frac{C}{{L + L_{\text{k}} }}} \left[ {\frac{{R_{\text{t}} + C_{\text{t}} + R_{\text{t}} C_{\text{t}} \left( {1 + \frac{{C_{d 0} }}{{C_{gi} }}} \right) + 0.5}}{{\sqrt {1 + C_{\text{t}} } }}} \right] + \frac{{\exp ( - 2.9\xi^{1.35} )}}{{\omega_{n} }}, $$
(20)
where
$$ \omega_{n} = \frac{1}{{\sqrt {(L + L_{\text{k}} )l(Cl + \theta C_{gi} )} }} $$
(21)
$$ \xi = \frac{{\left( {R_{\text{cnt}} l + 2R_{\text{ct}} } \right)}}{2}\sqrt {\frac{C}{{L + L_{\text{k}} }}} \left[ {\frac{{R_{\text{t}} + C_{\text{t}} + R_{\text{t}} C_{\text{t}} \left( {1 + \frac{{C_{d 0} }}{{C_{\text{gi}} }}} \right) + 0.5}}{{\sqrt {1 + C_{\text{t}} } }}} \right] $$
(22)
$$ R_{\text{t}} = \frac{{r_{d0} }}{{\theta (R_{\text{cnt}} l + 2R_{\text{ct}} )}} $$
(23)
$$ C_{\text{t}} = \frac{{\theta C_{gi} }}{Cl} $$
(24)
and Cd0, C gi and rd0 are the small-signal output capacitance (~ 0.032fF), input capacitance (~ 0.07fF) and output resistance (50 KΩ) of the minimum-sized gate in the interconnect line, respectively. θ is the ratio of driver or load size to minimum gate size.
Fig. 3

SWCNT interconnect with the optimum number of repeaters inserted to minimize the 50% delay time

An optimum number of repeaters are required to analyze the trade-off between time delay and repeater count. While considering the effect of inductance, delay time is linearly dependent on interconnect length [10]. In order to reduce the time delay of the response, an equi-spaced repeater can be included in the intermediate stages of the interconnect line [9]. In this section, the repeater insertion in SWCNT interconnects is studied and CMOS inverters are considered as repeaters, as shown in Fig. 3. An equivalent approach is followed to develop the formula for the optimum number of repeaters with less time delay. ηopt is the optimum number of repeaters required to achieve the minimum delay. From [16], we develop a formula for configuring the parasitics shown in Fig. 1. The line resistance (Rcnt) and contact resistance (Rct) occur due to a small imperfection between the nanotube and metal wires. l and rd0 are the length of the interconnect and internal resistance of the repeater, respectively. Cd0 and C gi are the small-signal capacitances of the CMOS repeater used in Eq. (25).
$$ \eta_{\text{opt}} = \text{int} \left[ {\sqrt {\frac{{(R_{\text{cnt}} l + 2R_{\text{ct}} )Cl}}{{2r_{d 0} (C_{d 0} + C_{gi} )}}} \frac{1}{{\left( {1 + \beta \psi^{3} } \right)^{0.28} }}} \right] - 1 $$
(25)
$$ \psi = \sqrt {\frac{{L + L_{\text{k}} }}{{R_{\text{cnt}} r_{d0} (C_{d0} + C_{gi} )}}} , $$
(26)
where ηopt is the optimum number of repeaters. In this work, the size of all CMOS repeaters is considered as equal, and the fitting parameter β has a unique value of 0.25 for SWCNT interconnect.

3 Results and Discussion

This section analyzes the delay of the SWCNT interconnect with respect to the optimum number of repeaters and interconnect length. The dependency of the optimum number of repeaters on interconnect length is observed with conventional copper (Cu) interconnects. The FDTD and empirical simulations are carried out using MATLAB, and the validations for different cases are done using HSPICE.

3.1 Delay Time Variation with Respect to Interconnect Length Without Repeaters

In this subsection, the variation of delay time as a function of interconnect length is studied, and it is observed that the time delays for copper and SWCNT interconnects vary linearly with the interconnect length. It is also observed that the delay time of SWCNT interconnects is less compared with copper interconnects. The primary reason behind this is the direct dependency of interconnect parasitics on delay time, as shown in Eq. (20). As the quantitative values of interconnect resistance and capacitance of copper are higher compared with SWCNT, the time constant of SWCNT is less, and this results in less time delay than copper interconnects. Using the transient response of Fig. 4, SWCNT exhibits lesser delay compared with copper interconnects. The simulation results are presented using FDTD in Eqs. (16) and (17a), and the results are validated with industry standard HSPICE simulations. As the technology changes from 16 to 32 nm, delay reduces, as delay time is inversely proportional to the parameter of size, as shown in Eq. (20). Hence, the proposed FDTD model predicts that the delay varies with ~ 4% tolerance with respect to HSPICE result, as shown in Table 1.
Fig. 4

Variation of delay time with respect to interconnect length: a 16-nm technology node and b 32-nm technology node without using repeaters

Table 1

Comparison of delays between Cu and SWCNT interconnect with respect to interconnect length

Interconnect length (µm)

16-nm technology node (ns)

% Error between FDTD and HSPICE for SWCNT

32-nm technology node (ns)

% Error between FDTD and HSPICE for SWCNT

Cu (HSPICE)

SWCNT (HSPICE)

SWCNT (FDTD)

Cu (HSPICE)

SWCNT (HSPICE)

SWCNT (FDTD)

10

3.2

2.3

2.24

2.6

2.2

1.5

1.55

− 2.5

100

12.35

10.5

10.9

− 3.8

10.6

8.3

8.45

− 1.8

200

26.35

20.6

21

− 1.94

26

16

16.34

− 2.15

400

47.45

31.2

31.4

− 0.6

42

24

24.1

− 0.41

600

59.45

41.3

41.6

− 0.72

59.45

35

35.1

− 0.285

800

81

75

76

− 1.3

82

62

61.7

0.48

1000

110

95

97

− 2.1

97

82

82.6

− 0.731

3.2 Selection of the Optimum Number of Repeaters Based on Interconnect Length

In any interconnect system, the time delay between the near and far ends is considered to be an important design constraint and depends on the interconnect length [10]. Repeater insertion is the best way to avoid delay between the source and the load. Therefore, it is of utmost importance to choose the correct number of repeaters in order to reduce the overall time delay. Figure 5a, b depicts the variation of repeater requirement for arbitrary interconnect lengths.
Fig. 5

Required number of repeaters depends on interconnect length and the material used for the interconnect: a 16-nm technology node and b 32-nm technology node

The dependent parameter l in Eq. (18) and the repeater’s small-signal impedances will determine the optimum number of repeaters needed to obtain minimum delay. In Fig. 5a, b, simulation results are presented for copper and SWCNT interconnects, which show that the number of repeaters required for copper is more compared with SWCNT for a given interconnect length. As the technology changes from 16 to 32 nm, the number of repeaters required reduces subsequently for both copper and SWCNT interconnects. The number of repeaters required is increased monotonically as a function of interconnect length, as shown in Table 2. If SWCNT interconnects are used instead of copper interconnects, the number of repeaters required is compressed by more than 40%.
Table 2

Number of repeaters required based on interconnect length and technology node

Interconnect length in (µm)

Optimum repeaters (η)

(16-nm technology node)

Interconnect length in (µm)

Optimum repeaters (η)

(32-nm technology node)

Copper (Cu)

SWCNT

Copper (Cu)

SWCNT

10

1

1

500

2

1

100

5

2

1000

3

1

200

8

2

1500

4

2

300

9

3

2000

4

2

400

11

3

2500

5

2

500

12

3

3000

5

3

600

13

4

3500

6

3

700

15

4

4000

6

3

800

16

4

4500

7

3

900

17

5

5000

8

4

1000

18

5

3.3 Interconnect Delay Analysis with Respect to Repeaters

In SWCNT interconnects, repeaters play a prominent role in reducing the 50% delay time; this is analyzed in this subsection. In Fig. 6a, b, it is observed that the number of repeaters exhibits an inverse relation with the time delay. For an interconnect length of 1000 µm, FDTD algorithm is applied to both Cu and SWCNT interconnects using superposition, as shown in Eq. (17b); this is validated using HSPICE, as shown in Eqs. (6a) and (6b) for 16- and 32-nm technology nodes, respectively. The power delay product (PDP) is also analyzed with respect to the number of repeaters and is shown in Fig. 7. It is observed that the PDP reduces to the optimum number of repeaters and later increases. The proposed algorithm obtains better prediction tending toward HSPICE, but with 4% tolerance, and the values are reported in Table 3.
Fig. 6

Variation of delay time with respect to the number of repeaters: a 16-nm technology node and b 32-nm technology node

Fig. 7

Variation of power delay product with respect to the number of repeaters

Table 3

Comparison of delays between Cu and SWCNT interconnects with respect to the number of repeaters and error using the proposed FDTD

Number of repeaters used (η)

Time delay (ns)

(16-nm technology node)

% Error between FDTD and HSPICE for SWCNT

Time delay (ns)

(32-nm technology node)

% Error between FDTD and HSPICE for SWCNT

Cu (HSPICE)

SWCNT (HSPICE)

SWCNT (FDTD)

Cu (HSPICE)

SWCNT (HSPICE)

SWCNT (FDTD)

2

9.3

3.34

3.4

− 1.8

10.4

3.62

3.69

− 1.93

4

6.3

2.305

2.38

− 3.25

7.3

2.78

2.81

− 1.08

6

4.32

1.89

1.91

− 1.06

6.1

2.21

2.25

− 1.81

8

3.18

1.663

1.7

− 2.22

4.2

1.83

1.91

− 4.37

10

2.43

1.544

1.53

0.91

3.2

1.62

1.69

− 4.3

An SWCNT interconnect length of 1000 µm is simulated for different numbers of repeaters in the intermediate stages, as shown in Fig. 8. Here, the number of repeaters inserted is increased by η = 2, 4, 6, 8 and 10, and the delay time at the far end is decreased accordingly, as depicted in Fig. 8. In Fig. 9, for η = 10 repeaters, the response at the output of each repeater along the interconnect line is depicted, and these responses are used to estimate the delay times, as shown in Eq. (17b). The effect of voltage excitation on time delay is reported in Table 4. As the magnitude of excitation increases, the delay time is reduced monotonically for a given number of repeaters. The power delay product is also reduced for minimum voltage magnitude and is based on the square-law proportionality between power and excitation magnitude, as reported in Table 4.
Fig. 8

Output at the far end of the interconnect by varying the number of repeaters at the intermediate stages

Fig. 9

Output at the end of each intermediate repeater stage in a chain of 10 repeaters

Table 4

Delay time variation with respect to voltage and repeater variations

Number of repeaters (η)

Delay for different supply voltages (ns)

0.8 V

0.75 V

0.7 V

0.65 V

0.6 V

0.55 V

0.5 V

2

3.322

3.334

3.348

3.379

3.442

3.558

3.778

4

2.269

2.283

2.305

2.343

2.413

2.532

2.746

6

1.857

1.869

1.890

1.972

1.991

2.103

2.295

8

1.629

1.640

1.663

1.698

1.757

1.860

2.041

10

1.558

1.573

1.594

1.631

1.694

1.798

1.979

Power delay product

0.335

0.208

0.124

0.072

0.043

0.026

0.018

Figures 8 and 9 are the output waveforms of SWCNT interconnect-based system with CMOS driver, repeaters and load. We inserted 10 CMOS repeaters in SWCNT-based interconnect line and applied logic 1 (0–0.7 V) as input to the CMOS driver and observed logic 0 (0.7–0 V) as output for each even number of repeaters (2, 4, 6, 8 and 10) at the intermediate stage of SWCNT interconnect line. In Fig. 8, we plotted the output for each stage of even number of repeaters and observed the reduction in signal delay. Similarly, in Fig. 9, we also plotted the output of each single repeater in an interconnect line and observed the effect of repeaters on signal delay. The signal time delays are noted and shown in Table 3, by varying the number of repeaters for Cu and SWCNT interconnect line.

4 Conclusion

The proposed highly accurate transient time FDTD model satisfied an extreme accuracy limit of 97% to the predicted delay time at the far end of the interconnect and is validated by inserting the optimal number of repeaters and no repeaters in the intermediate stage. It is also proved that a longer interconnect length is the cause of delay in the transient period, and the best solution to this is to incorporate the optimum number of repeaters in it. The responses obtained using FDTD is the same compared with empirical formula and HSPICE simulations. Further, it is demonstrated that the optimum number of repeaters required for SWCNT interconnects is reduced by more than 40% compared with copper interconnects, and the repeater insertion improves transient performance in terms of delay time.

References

  1. 1.
    A. Afrooz, Time domain analysis of field effect transistors using unconditionally stable finite difference method. IET Sci. Meas. Technol. 10(7), 686–692 (2016)CrossRefGoogle Scholar
  2. 2.
    K. Afrooz, A. Abdipour, Efficient method for time-domain analysis of lossy nonuniform multiconductor transmission line driven by a modulated signal using FDTD technique. IEEE Trans. Electromagn. Compat. 54(2), 482–494 (2012)CrossRefGoogle Scholar
  3. 3.
    K. Agarwal, D. Sylvester, D. Blaauw, Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5), 892–901 (2006)CrossRefGoogle Scholar
  4. 4.
    N.W. Ashcroft, N.D. Mermin, Solid State Physics (Saunders College, Philadelphia, 1976)zbMATHGoogle Scholar
  5. 5.
    K. Banerjee, A. Mehrotra, A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans. Electron Dev. 49(11), 2001–2007 (2002)CrossRefGoogle Scholar
  6. 6.
    D. Das, H. Rahaman, Analysis of crosstalk in single- and multiwall carbon nanotube interconnects and its impact on gate oxide reliability. IEEE Trans. Nanotechnol. 10(6), 1362–1370 (2011)CrossRefGoogle Scholar
  7. 7.
    R. Dhiman, R. Chandel, Dynamic crosstalk analysis in coupled interconnects for ultra-low power applications. Circuits Syst. Signal Process. 34, 21–40 (2015).  https://doi.org/10.1007/s00034-014-9853-y MathSciNetCrossRefGoogle Scholar
  8. 8.
    N. Farahat, H. Raouf, R. Mittra, Analysis of interconnect lines using the finite-difference time-domain (FDTD) method. Microw. Opt. Technol. Lett. 34(1), 6–9 (2002)CrossRefGoogle Scholar
  9. 9.
    A. Giustiniani, V. Tucci, W. Zamboni, Modeling issues and performance analysis of high-speed interconnects based on a bundle of SWCNT. IEEE Trans. Electron Dev. 57(8), 1978–1986 (2010)CrossRefGoogle Scholar
  10. 10.
    Y.I. Ismail, E.G. Friedman, Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 8(2), 195–206 (2000)CrossRefGoogle Scholar
  11. 11.
    B.K. Kaushik, S. Sarkar, R.P. Agarwal, R.C. Joshi, Crosstalk analysis of simultaneously switching interconnects. Int. J. Electron. 96(10), 1095–1114 (2009)CrossRefGoogle Scholar
  12. 12.
    V.R. Kumar, B.K. Kaushik, A. Patnaik, An unconditionally stable FDTD model for crosstalk analysis of VLSI interconnects. IEEE Trans. Compon. Packag. Manuf. Technol. 5(12), 1810–1817 (2015)CrossRefGoogle Scholar
  13. 13.
    X. Li, J. Mao, M. Swaminathan, Analysis of frequency-dependent lossy transmission lines driven by CMOS gates, in IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) (Shatin, Hong Kong, 2009), pp. 1–4Google Scholar
  14. 14.
    H. Li, C. Xu, N. Srivastava, K. Banerjee, Carbon nanomaterials for next-generation interconnects and passives: physics, status, and prospects. IEEE Trans. Electron Dev. 56(9), 1799–1821 (2009)CrossRefGoogle Scholar
  15. 15.
    X. Li, J. Mao, M. Swaminathan, Transient analysis of CMOS gate-driven RLGC interconnects based on FDTD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4), 574–583 (2011)CrossRefGoogle Scholar
  16. 16.
    F. Liang, G. Wang, W. Ding, Estimation of time delay and repeater insertion in multiwall carbon nanotube interconnects. IEEE Trans. Electron Dev. 58(8), 2712–2720 (2011)CrossRefGoogle Scholar
  17. 17.
    F. Liang, G. Wang, H. Lin, Modeling of crosstalk effects in multiwall carbon nanotube interconnects. IEEE Trans. Electromagn. Compat. 54(1), 133–139 (2012)CrossRefGoogle Scholar
  18. 18.
    A. Naeemi, J.D. Meindl, Carbon nanotube interconnects. Annu. Rev. Mater. Res. 39, 255–275 (2009)CrossRefGoogle Scholar
  19. 19.
    A. Pal, A. Chaudhuri, R.K. Pal, A.K. Datta, Hardness of crosstalk minimization in two-layer channel routing. Integr. VLSI J. 56, 139–147 (2017)CrossRefGoogle Scholar
  20. 20.
    J.D. Pursel, P.M. Goggans, A finite-difference time-domain method for solving electromagnetic problems with bandpass-limited sources. IEEE Trans. Antenna Propag. 47(1), 9–15 (1999)MathSciNetCrossRefzbMATHGoogle Scholar
  21. 21.
    C. Rutherglen, P.J. Burke, Nanoelectromagnetics: circuit and electromagnetic properties of carbon nanotubes. Small 5(8), 884–906 (2009)CrossRefGoogle Scholar
  22. 22.
    A. Taflove, Computational Electrodynamics (Artech House, Norwood, 1995)zbMATHGoogle Scholar
  23. 23.
    R. Venkatesan, J.A. Davis, J.D. Meindl, Compact distributed RLC interconnect models—part IV: unified models for time delay, crosstalk, and repeater insertion. IEEE Trans. Electron Dev. 50(4), 1094–1102 (2003)CrossRefGoogle Scholar
  24. 24.
    Q. Xu, Z.F. Li, J. Wang, J.F. Mao, Transient analysis of lossy interconnects by modified method of characteristics. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 47(3), 363–375 (2000)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • C. Venkataiah
    • 1
    • 2
  • K. Satyaprasad
    • 1
    • 3
  • T. Jayachandra Prasad
    • 2
  1. 1.Jawaharlal Nehru Technological UniversityKakinadaIndia
  2. 2.Rajeev Gandhi Memorial College of Engineering and TechnologyNandyalIndia
  3. 3.KL UniversityGunturIndia

Personalised recommendations