Skip to main content
SpringerLink
Log in

Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

Floating-point addition is the most frequently used arithmetic operation in almost all general-purpose processors. This paper presents a dual-mode architecture for fused floating-point three-term adder. The traditional architecture for fused floating-point three-term adder is single-mode design where the addition of three operands takes place in a single unit. The existing improved architecture is also a single-mode design that incorporates few optimizations compared to the traditional fused floating-point three-term adder that would reduce area as well as delay. The proposed dual-mode architecture performs either a double-precision addition or two parallel single-precision additions in a single architecture based on the mode selection. The proposed architecture supports both normal and subnormal operations and also exceptional case handling like infinity, NaN and zero cases. The proposed architecture is implemented using both FPGA and ASIC, thus leading to efficient resource sharing, and the area gets reduced compared to two single-precision and a double-precision traditional and improved floating-point adder architectures.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. A. Akkas, Dual-mode floating-point adder architectures. J. Syst. Archit. 54(12), 1129–1142 (2008)

    Article  Google Scholar 

  2. A. Akkas, Dual-mode quadruple precision floating-point adder, in Proceedings of the Euromicro Symposium Digital System (DSD’06) (2006), pp. 211–220

  3. J.D. Bruguera, T. Lang, Floating-point fused multiply-add: reduced latency for floating-point addition, in 17th IEEE Symposium on Computer Arithmetic (2005), pp. 42–51

  4. S. Galal, M. Horowitz, Energy-efficient floating-point unit design. IEEE Trans. Comput. 60(7), 913–922 (2011)

    Article  MathSciNet  MATH  Google Scholar 

  5. Y. Hida, X.S. Li, D.H. Bailey, Algorithms for quad-double precision floating point arithmetic, in Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 (2001), pp. 155–162

  6. IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE, 1985)

  7. IEEE standard 754-2008, IEEE Standard for Floating-Point Arithmetic. Technical Report (2008), pp. 1–70

  8. M.K. Jaiswal, R.C.C. Cheung, M. Balakrishnan, Unified architecture for double/two-parallel single precision floating point adder. IEEE Trans. Circuits Syst. 61(7), 521–525 (2014)

    Article  Google Scholar 

  9. T. Lang, J.D. Bruguera, Floating-point multiply-add-fused with reduced latency. IEEE Trans. Comput. 53(8), 988–1003 (2004)

    Article  Google Scholar 

  10. G. Marcus, P. Hinojosa, A. Avila, J. Nolazco-FIores, A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use, in Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems (2004), pp. 319–323

  11. V.G. Oklobdzija, An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. IEEE Trans. Very Large Scale Integr. VLSI Syst. 2(1), 124–128 (1994)

    Article  Google Scholar 

  12. H. Saleh, E.E. Swartzlander, A floating-point fused add-subtract unit, in 51st Midwest Symposium on Circuits and Systems (2008), pp. 519–522

  13. H.H. Saleh, E.E. Swartzlander, A floating-point fused dot product unit, in Proceedings of the IEEE International Conference Computer Design (2008), pp. 427–431

  14. E.M. Schwarz, M. Schmookler, S.D. Trong, Hardware implementations of denormalized numbers, in Proceedings of the 16th IEEE Symposium on Computer Arithmetic Metic (2003), pp. 70–78

  15. P.M. Seidel, G. Even, Delay-optimized implementation of IEEE floating-point addition. IEEE Trans. Comput. 53(2), 97–113 (2004)

    Article  Google Scholar 

  16. J. Sohn, E.E. Swartzlander, Improved architectures for a fused floating-point add-subtract unit. IEEE Trans. Circuits Syst. I Reg. Pap. 59(10), 2285–2291 (2012)

    Article  MathSciNet  Google Scholar 

  17. J. Sohn, E.E. Swartzlander, A fused floating-point three-term adder. IEEE Trans. Circuits Syst. I Regul. Pap. 61(10), 2842–2850 (2014)

    Article  MathSciNet  Google Scholar 

  18. E.E. Swartzlander, H.H. Saleh, Fused floating-point arithmetic for DSP, in Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers (2008), pp. 767–771

  19. Y. Tao, G. Deyuan, F. Xiaoya, R. Xianglong, Three-operand floating-point adder, in IEEE 12th International Conference on Computer and Information Technology (2012), pp. 192–196

  20. A.F. Tenca, Multi-operand floating-point addition, in Proceedings of the 19th IEEE Symposium on Computer Arithmetic (ARITH ‘09) (2009), pp. 161–168

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Anna University Regional Campus, Coimbatore, Tamil Nadu, India

    K. Thiruvenkadam & Anjali S. Pillai

  2. Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore, Tamil Nadu, India

    J. Ramesh

Authors
  1. K. Thiruvenkadam
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. J. Ramesh
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Anjali S. Pillai
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to K. Thiruvenkadam.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Thiruvenkadam, K., Ramesh, J. & Pillai, A.S. Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder. Circuits Syst Signal Process 38, 173–190 (2019). https://doi.org/10.1007/s00034-018-0848-y

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-018-0848-y

Keywords

Search

Navigation