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Algorithmica

, Volume 18, Issue 3, pp 384–404 | Cite as

An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem

  • Vijaya Ramachandran
  • Honghua Yang

Abstract.

A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. A layered PMC is a PMC in which all input nodes are in the external face, and the gates can be assigned to layers in such a way that every wire goes between gates in successive layers. Goldschlager, Cook and Dymond, and others have developed NC 2 algorithms to evaluate a layered PMC when the output node is in the same face as the input nodes. These algorithms require a large number of processors (Ω(n 6 ), where n is the size of the input circuit).

In this paper we give an efficient parallel algorithm that evaluates a layered PMC of size n in \(O(\log^2 n)\) time using only a linear number of processors on an EREW PRAM. Our parallel algorithm is the best possible to within a polylog factor, and is a substantial improvement over the earlier algorithms for the problem.

Key words. Circuit value problem, Planar monotone circuit, Plane graph, Parallel algorithm, EREW PRAM. 

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Copyright information

© Springer-Verlag New York Inc. 1997

Authors and Affiliations

  • Vijaya Ramachandran
    • 1
  • Honghua Yang
    • 1
  1. 1.Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712, USA. vlr@cs.utexas.edu. yanghh@cs.utexas.edu.US

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