International Journal of Parallel Programming

, Volume 24, Issue 2, pp 159–186 | Cite as

Evaluating the Effects of Predicated Execution on Branch Prediction



As microprocessor designs move towards deeper pipelines and support for multiple instruction issue, steps must be taken to alleviate the negative impact of branch operations on processor performance. One approach is to use branch prediction hardware and perform speculative execution of the instructions following an unresolved branch. Another technique is to eliminate certain branch instructions altogether by translating the instructions following a forward branch into predicate form. Both these techniques are employed in many current processor designs. This paper investigates the relationship between branch prediction techniques and branch predication. In particular, we are interested in how using predication to remove a certain class of poorly predicted branches affects the prediction accuracy of the remaining branches. A variety of existing predication models for eliminating branch operations are presented, and the effect that eliminating branches has on branch prediction schemes ranging from simple prediction mechanisms to the newer more sophisticated branch predictors is studied. We also examine the impact of predication on basic block size, and how the two techniques used together affect overall processor performance.

Key Words

Predication branch prediction PA-RISC alpha ATOM Pentium PowerPC 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    J. E. Smith, A Study of Branch Prediction Strategies, Proc. of the Eighth Annual Int. Symp. on Computer Architecture, Minneapolis, Minnesota, pp. 135–148 (May 1981).Google Scholar
  2. 2.
    J. K. L. Lee and A. J. Smith, Branch Prediction Strategies and Branch Target Buffer Design, Computer, 17(1):6–22 (January 1984).CrossRefGoogle Scholar
  3. 3.
    J. A. Fisher and S. M. Freudenberger, Predicting Conditional Branch Directions from Previous Runs of a Program, Proc. of the Fifth Int. Conf. on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, pp. 85–95 (October 12–15, 1992).CrossRefGoogle Scholar
  4. 4.
    T. Yeh and Y. Patt, A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History, Proc. of the 20th Ann. Int. Symp. on Computer Architecture, San Diego, California, pp. 257–266 (May 16–19, 1993).CrossRefGoogle Scholar
  5. 5.
    R. M. Russell, The CRAY-1 Computer System, Comm. ACM, 21(1):63–72 (January 1978).CrossRefGoogle Scholar
  6. 6.
    P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Warter, and W. Hwu, IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors, Proc. of the 18th Ann. Int. Symp. on Computer Architecture, Toronto, Canada, pp. 266–275 (May 27–30, 1991).Google Scholar
  7. 7.
    J. C. Dehnert, P. Y. T. Hsu, and J. P. Bratt, Overlapped Loop Support for the Cydra 5, Proc. of the 17th Ann. Symp. on Computer Architecture, pp. 26–38 (May 1989).Google Scholar
  8. 8.
    T. Asprey, G. S. Averill, E. DeLano, R. Mason, B. Weiner, and J. Yetter, Performance Features of the PA7100 Microprocessor, IEEE Micro, pp. 22–35 (June 1993).Google Scholar
  9. 9.
    E. McLellan, The Alpha AXP Architecture and 21064 Processor, IEEE Micro, pp. 35–47 (June 1993).Google Scholar
  10. 10.
    R. L. Sites, Alpha Architecture Reference manual, Digital Press (1992).Google Scholar
  11. 11.
    D. Alpert and D. Avnon, Architecture of the Pentium Microprocessor, IEEE Micro, pp. 11–21 (June 1993).Google Scholar
  12. 12.
    PowerPC 601 RISC Microprocessor User’s Manual Addendum for 604, Motorola/IBM Microelectronics (1993, 1994).Google Scholar
  13. 13.
    T. Yeh and Y. Patt, Two-Level Adaptive Training Branch Prediction, Proc. of the 24th Ann. Int. Symp. on Microarchitecture, Albuquerque, New Mexico, pp. 51–61 (November 18–20, 1991).CrossRefGoogle Scholar
  14. 14.
    B. R. Rau, D. W. L. Yen, W. Yen, and R. A. Towle, The Cydra 5 Departmental Supercomputer, IEEE Computer, pp. 12–35 (January 1989).Google Scholar
  15. 15.
    D. N. Pnevmatikatos and G. S. Sohi, Guarded Execution and Branch Prediction in Dynamic ILP Processors, Proc. of the 21st Ann. Int. Symp. on Computer Architecture, Chicago, Illinois, pp. 120–129 (April 18–21, 1994).CrossRefGoogle Scholar
  16. 16.
    J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufman, San Mateo, California, (1990).MATHGoogle Scholar
  17. 17.
    A. Srivastava and A. Eustace, ATOM: A System for Building Customized Program Analysis Tools, Proc. of the ACM SIGPLAN Notices Conf. on Programming Languages and Implementations, pp. 196–205 (June 1994).Google Scholar
  18. 18.
    J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, Second Edition, Morgan Kaufman, San Francisco, California, (1996).MATHGoogle Scholar
  19. 19.
    S. A. Mahlke, R. E. Hank, R. A. Bringmann, J. C. Gyllenhaal, D. M. Gallagher, and W. W. Hwu, Characterizing the Impact of Predicated Execution on Branch Prediction, Proc. of the 27th Ann. Int. Symp. on Microarchitecture, San Jose, California, pp. 217–227 (November 30–December 2, 1994).Google Scholar
  20. 20.
    G. Tyson, M. Farrens, K. Rich, and A. Pleszkun, Reducing the Branch Penalty of Mispredicted Short Forward Branches, Computer Science Department Technical Report CSE-95-7, University of California, Davis, Davis, California (August 1995).Google Scholar

Copyright information

© Plenum Publishing Corporation 1996

Authors and Affiliations

  1. 1.Department of Computer ScienceUniversity of California, RiversideRiversideUSA
  2. 2.Department of Computer ScienceUniversity of California, DavisDavisUSA

Personalised recommendations