Advertisement

New Generation Computing

, Volume 2, Issue 1, pp 37–58 | Cite as

Highly parallel inference engine PIE —Goal rewriting model and machine architecture—

  • Atsuhiro Goto
  • Hidehiko Tanaka
  • Tohru Moto-Oka
Regular Papers

Abstract

Logic programming is expected to make knowledge information processing feasible. However, conventional Prolog systems lack both processing power and flexibility for solving large problems. To overcome these limitations, an approach is developed in which natural execution features of logic programs can be represented using Proof Diagrams. AND/ OR parallel processing based on a goal-rewriting model is examined. Then the abstract architecture of a highly parallel inference engine (PIE) is described. PIE makes it possible to achieve logic/control separation in machine architecture. The architecture proposed here is discussed from the viewpoint of its high degree of parallelism and flexibility in problem solving in comparison with other approaches.

Keywords

Parallel Inference Machine 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1).
    Boyer, R. S. and Moore, J. S.: “The Sharing of Structure in Theorem-proving Progams”, Machine Intelligence,7 (1972) 101–116.MATHGoogle Scholar
  2. 2).
    Chakravarthy, U.S., et al.: “Interfacing Predicate Logic Languages and Relational Databases”, Proc. of First International Logic Programming Conference (Sept., 1982) 91–98.Google Scholar
  3. 3).
    Ciepielewski, A. and Haridi, S.: “A Formal Model for Or-Parallel Execution of Logic Programs”, Information Processing 83 (Sept., 1983) 299–306.Google Scholar
  4. 4).
    Ciepielewski, A. and Haridi, S.: “Control of Activities in an OR-Parallel Token Machine”, Proceeding of Logic Programming Workshop ’83 (July, 1983) 536.Google Scholar
  5. 5).
    Clark, K. L. and Gregory, S.: “A Relational Language for Parallel Programming”, Proc. of the 1981 Conf. on Functional Programming Languages and Computer Architecture (Oct., 1981).Google Scholar
  6. 6).
    Conery, J. S. and Kibler, D. F.: “Parallel Interpretation of Logic Programs”, Proc. of the 1981 Conf. on Functional Programming Languages and Computer Architecture (Oct., 1981) 163–170.Google Scholar
  7. 7).
    Darlington, J. and Reeve, M.: “ALICE: A Multi-Processor Reduction Machine for the Parallel Evaluation of Applicative Languages”, Proc. of the 1981 Conf. on Functional Programming Languages and Computer Architecture (Oct., 1981) 65–76.Google Scholar
  8. 8).
    van Emden, M. H.: “An Algorithm for Interpreting Prolog Programs”, Proc. of First International Logic Programming Conference (Sept., 1982) 56–64.Google Scholar
  9. 9).
    Kasif, S., Kohli, M., and Minker, J.: “PRISM: A Parallel Inference System for Problem Solving”, Proceeding of Logic Programming Workshop ’83 (July, 1983) 123–152.Google Scholar
  10. 10).
    Kowalski, R.: “Logic Programming”, Information Processing 83 (Sept., 1983) 133–146.Google Scholar
  11. 11).
    Moto-oka, T. (ed.): Proceeding of International Conference of Fifth Generation Computer System (Oct., 1981).Google Scholar
  12. 12).
    Nilsson, N. J.: Principle of Artificial Intelligence (Tioga Publishing Company, 1980).Google Scholar
  13. 13).
    Shapiro, E. Y.: “A Subset of Concurrent Prolog and its Interpreter”, ICOT Technical Report,TR-003 (ICOT, 1983).Google Scholar
  14. 14).
    Umeyama, S. and Tamura, K.: “A Parallel Execution Model of Logic Programs”, The 10th Annual International Symposium on Computer Architecture, ACM (June, 1983) 349–355.Google Scholar
  15. 15).
    Warren, D. H. D.: “Implementing Prolog — compiling predicate logic programs”, D. A. I. Research Report,39–40 (1977).Google Scholar
  16. 16).
    Goto, A., et al.: “On the Efficient Parallel Processing of the Highly Parallel Inference Engine — PIE”, IECEJ Technical Group Meeting,EC83-9 (May, 1983) [in Japanese].Google Scholar

Copyright information

© Ohmsha, Ltd. and Springer 1984

Authors and Affiliations

  • Atsuhiro Goto
    • 1
  • Hidehiko Tanaka
    • 1
  • Tohru Moto-Oka
    • 1
  1. 1.Department of Electrical Engineering, Faculty of EngineeringThe University of TokyoTokyoJapan

Personalised recommendations