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Annales Des Télécommunications

, Volume 48, Issue 11–12, pp 537–545 | Cite as

Une mÉthode analogique de test des circuits et des systÉmes intÉgres massivement parallÉles: Application au test des rÉseaux neuronaux

  • Kurosh Madani
Article
  • 19 Downloads

Résumé

LĽaccroissement de la densité dď intégration dďune part, et de la complexité des circuits et des systémes intégrés modernes dďautre part, ont révélé la necessity de prendre en compte les problémes de test au niveau même de la conception de ces derniers. Dans cet article, lľauteur propose une technique analogique de test des circuits et des systémes intégrés à sorties numériques massivement paralléles, basée sur une mesure du courant. Cette technique permet le test simultané dďun grand nombre de cellules dďun circuit intégré et de ce fait est attractive pour le test des réseaux neuronaux. Des résultats de simulation sont présentés.

Mots clés

Méthode essai Circuit intégré Systéme paralléle Réseau neuronal Testabilité Circuit numérique 

An analogue test technique for massively parallel integrated circuits and systems: An approach to neural networks circuits testing

Abstract

The increase in integration density and in complexity of moderns integrated circuits and systems revealed the necessity to consider the testability problem at the design level of circuits. One of the most active research areas in circuits design, over the past decade, has been the implementation of neural networks as electronic VLSI chips. Especially, the implementation of artificial neural networks (ANN) as CMOS integrated circuits shows several attractive features. Recent studies point out that classification is their most successful application field, and thus large networks will be required. Unfortunately, very few papers analyse the testability of electronic implementation of artificial neural networks. A large number of artificial neural networks models deal with binary output neurones. This paper presents and discuss a global current measurement based pseudo-analogue technique for digital-output electronic neural networks testing. Two approaches have been presented and their limitations have been discussed. Simulation results and a method validation test circuit have been presented.

Key words

Test method Integrated circuit Parallel system Neural network Testability Digital circuit 

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Copyright information

© Springer-Verlag 1993

Authors and Affiliations

  • Kurosh Madani
    • 1
  1. 1.LERISS/TMS, groupe de conception, modélisation, test et fiabilitéUniversité Paris XIILieusaintFrance

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