Advertisement

Journal of Computer Science and Technology

, Volume 15, Issue 5, pp 472–479 | Cite as

Exploiting deterministic TPG for path delay testing

  • Li Xiaowei Email author
  • Paul Y. S. Cheung
Article

Abstract

Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for path delay testing. Given a set of pre-generated test-pairs with pre-determined fault coverage, a deterministic TPG is synthesized to apply the given test-pair set in a limited test time. To achieve this objective, configurable linear feedback shift register (LFSR) structures are used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is very efficient in terms of hardware size and speed performance. Simulation of academic benchmark circuits has given good results when compared to alternative solutions.

Keywords

built-in self-test (BIST) path delay testing deterministic TPG configurable LFSR 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Voyiatzis I, Paschalis A, Nikolos Det al. Accumulator-based BIST approach for stuck-open and delay fault testing. In Proc. IEEE European Design and Test Conf. (EURO DTC’95), 1995, pp. 432–435.Google Scholar
  2. [2]
    Pilarski S, Pierzyriska A. BIST and delay fault detection. InProc. IEEE Int. Test. Conf. (ITC’93), 1993, pp.236–242.Google Scholar
  3. [3]
    Furuya K, McClusky E J. Two-pattern test capability of autonomous TPG circuits. InProc. IEEE Int. Test Conf. (ITC’91), 1991, pp.704–711.Google Scholar
  4. [4]
    Girard P, Landrault C, Moreda V, Pravossoudovitch S. An optimized BIST test pattern generator for delay testing. InProc. IEEE VLSI Test Symposium (VTS’97), 1997, pp.94–100.Google Scholar
  5. [5]
    Li X, Cheung P Y S. Exploiting BIST approach for two-pattern testing. InProc. IEEE Asian Test Symposium (ATS’98), 1998, pp.424–429.Google Scholar
  6. [6]
    Chen C-A, Gupta S K. BIST test pattern generators for two-pattern testing: Theory and design algorithms.IEEE Trans. Computers, 1996, 45(3): 257–269.zbMATHCrossRefMathSciNetGoogle Scholar
  7. [7]
    Dufaza C, Zorian Y. On the generation of pseudo-deterministic two-pattern test sequence with LFSRs. InProc. IEEE European Design, and Test Conf. (EURO DTC’97), 1997, pp.69–76.Google Scholar
  8. [8]
    Starke C W. Built-in test for CMOS circuits. InProc. IEEE Int. Test Conf. (ITC’84), 1984, pp.309–314.Google Scholar
  9. [9]
    Wurth B, Fuchs K. A BIST approach to delay fault testing with reduced test length. InProc. IEEE European Design and Test Conf. (EURO DTC’95), 1995, pp.418–423.Google Scholar
  10. [10]
    Zhang S, Byrne R, Miller D M. BIST generators for sequential faults. InProc. IEEE Int. Conf. Computer Design (ICCD’92), 1992, pp.260–263.Google Scholar
  11. [11]
    Golomb S W, Welch L R, Goldstein R Met al. Shift Register Sequences. Aegean park Press, 1982.Google Scholar
  12. [12]
    Shi C J, Brzozowski J A. Cluster-cover: A theoretical framework for a class of VLSI-CAD optimization problem.ACM Trans. Design Automation of Electronic Systems, 1998, 3(1): 76–107.CrossRefGoogle Scholar
  13. [13]
    Brglez F, Bryan D, Kozminski K. Combinational profile of sequential benchmark circuits. InProc. IEEE Int. Symposium on Circuits and Systems (ISCAS’98), 1998, pp.1929–1934.Google Scholar

Copyright information

© Science Press, Beijing China and Allerton Press Inc. 2000

Authors and Affiliations

  1. 1.Department of Computer SciencePeking UniversityBeijingP.R. China
  2. 2.Department of Electrical and Electronic EngineeringThe University of Hong KongHong Kong, P.R. China

Personalised recommendations