Journal of Computer Science and Technology

, Volume 15, Issue 5, pp 472–479 | Cite as

Exploiting deterministic TPG for path delay testing

  • Li Xiaowei Email author
  • Paul Y. S. Cheung


Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for path delay testing. Given a set of pre-generated test-pairs with pre-determined fault coverage, a deterministic TPG is synthesized to apply the given test-pair set in a limited test time. To achieve this objective, configurable linear feedback shift register (LFSR) structures are used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is very efficient in terms of hardware size and speed performance. Simulation of academic benchmark circuits has given good results when compared to alternative solutions.


built-in self-test (BIST) path delay testing deterministic TPG configurable LFSR 


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Copyright information

© Science Press, Beijing China and Allerton Press Inc. 2000

Authors and Affiliations

  1. 1.Department of Computer SciencePeking UniversityBeijingP.R. China
  2. 2.Department of Electrical and Electronic EngineeringThe University of Hong KongHong Kong, P.R. China

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