Abstract
Area and test time are two major overheads encountered during data path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of the BIST scheme during behavioral synthesis processes, an area optimal BIST solution can be obtained. This approach is based on the use of test resources reusability that results in a fewer number of resiters being modified to be test registers. This is achieved by incorporating self-testability constraints during register assignment operations. Experimental results on benchmarks are presented to demonstrate the effectiveness of the approach.
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This work was supported in part by the National Natural Science Foundation of China (NSFC) under grant No. 69976002 and in part by the Croucher Foundation under grant No.360/062/0994.
LI Xiaowei received his B.Eng. and M.Eng. degrees in computer science from Hefei University of Technology, China, in 1985 and 1988, respectively. He received his ph.D. degree in computer science from the Institute of Computing Technology, the Chinese Academy of Sciences in 1991. Dr. Li joined Peking University as a Postdoctoral Research Fellow and a Lecturer in 1991, and was promoted to Associate Professor in 1993, all with the Department of Computer Science and Technology. In 1997 and 1998, he was a Visiting Research Fellow in the Department of Electrical and Electronic Engineering at the University of Hong Kong. In 1999, he was a Visiting Professor in the Graduate School of Information Science, Nara Institute of Science and Technology, Japan. His research interests include VLSI testing, design for testability, built-in self-test, high-level synthesis for testability, software testing and hardware/software co-test.
Paul Y.S. CHEUNG received his B.S. (Eng) degree with first-class honor in 1973 and his Ph.D. degree in 1978, both in EE from the Imperial College of Science and Technology, University of London. After working for Queen’s University of Belfast for two years as an engineer-in-charge of a laboratory, he returned to Hong Kong in 1978 to take up an academic position at the Hong Kong Polytechnic University. He joined the University of Hong Kong as a lecturer in 1980 and was promoted to Senior Lecturer/Associate Professor in 1987. He served as the Associate Dean of Faculty of Engineering from 1991–1994 and has been the Dean of Faculty of Engineering at the University of Hong Kong since 1994. He was the Director of IEEE Asia Pacific in 1995–1996 and served as the Secretary of IEEE in 1997. His research interests include parallel computer architecture, Internet computing, VLSI design and testing, signal processing and pattern recognition.
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Li, X., Cheung, P.Y.S. High level synthesis for loop-based BIST. J. Comput. Sci. & Technol. 15, 338–345 (2000). https://doi.org/10.1007/BF02948869
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DOI: https://doi.org/10.1007/BF02948869