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A maximum time difference pipelined arithmetic unit based on CMOS gate array

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Abstract

This paper describes a maximum time difference pipelined arithmetic chip, the 36-bit adder and subtractor based on 1.5 μm CMOS gate array. The chip can operate at 60MHz, and consumes less than 0.5 Watt. The results are also studied, and a more precise model of delay time difference is proposed.

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References

  1. Cotten L. Maximum rate pipelined systems. In1969 AFIPS Proceeding of Spring Joint Computer Conference, pp. 581–586.

  2. Goldberg D. Computer arithmetic. InComputer Architecture: A Quantitative Approach, Hennessy J L & Patterson D A (eds.), Morgan Kaufmann Publishers, Inc., 1990, pp. A1–A66.

  3. Klass F, Mulder J M. Use of CMOS technology in wave pipelining. InProceedings of the Fifth Conference on VLSI Design, Bangalore, India, January, 1992, pp. 303–308.

  4. Lin Qi, Xia Peisu. The design and implementation of a very fast experimental pipelining computer.Journal of Computer Science and Technology, 1988, 3(1): 1–6.

    Article  Google Scholar 

  5. Weste N, Eshraghian K. Principles of CMOS VLSI Design. Addison-Wesley, 1985.

  6. Wong D Cet al., Designing high performance digital circuits using wave pipelining: Algorithms and practical experiences.IEEE Transcations on Computer-Aided Design of Ingegrated Circuits and Systems, 1993, 12(1): 25–46.

    Article  Google Scholar 

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Authors and Affiliations

  1. Institute of Computing Technology, The Chinese Academy of Sciences, 100080, Beijing

    Tang Zhimin & Xia Peisu

Authors
  1. Tang Zhimin
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  2. Xia Peisu
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Corresponding author

Correspondence to Tang Zhimin.

Additional information

Project supported by National Natural Science Foundation of China under grant No.9689009.

Tang Zhimin received his B.S. degree from Nanjing University in 1985 and his Ph.D. degree from the Institute of Computing Technology, the Chinese Academy of Sciences in 1990, both in computer science. He is currently a Professor of the Institute of Computing Technology. His research interests include high performance computer architecture, parallel computing and VLSI design.

Xia Peisu is a member of the Chinese Academy of Sciences and a Professor of the Institute of Computing Technology. She received her Ph.D. degree in electrical engineering from University of Edinburgh, United Kindom, in 1950. Her current research interests include computer architecture, computer engineering, high, speed pipeline system and parallel processing.

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Tang, Z., Xia, P. A maximum time difference pipelined arithmetic unit based on CMOS gate array. J. of Comput. Sci. & Technol. 10, 97–103 (1995). https://doi.org/10.1007/BF02948419

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  • DOI: https://doi.org/10.1007/BF02948419

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