Journal of Computer Science and Technology

, Volume 10, Issue 2, pp 97–103 | Cite as

A maximum time difference pipelined arithmetic unit based on CMOS gate array

  • Tang Zhimin Email author
  • Xia Peisu 
Regular Papers


This paper describes a maximum time difference pipelined arithmetic chip, the 36-bit adder and subtractor based on 1.5 μm CMOS gate array. The chip can operate at 60MHz, and consumes less than 0.5 Watt. The results are also studied, and a more precise model of delay time difference is proposed.


Adder CMOS gate array maximum time difference wave pipeline 


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Copyright information

© Science Press, Beijing China and Allerton Press Inc. 1995

Authors and Affiliations

  1. 1.Institute of Computing TechnologyThe Chinese Academy of SciencesBeijing

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