A maximum time difference pipelined arithmetic unit based on CMOS gate array
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This paper describes a maximum time difference pipelined arithmetic chip, the 36-bit adder and subtractor based on 1.5 μm CMOS gate array. The chip can operate at 60MHz, and consumes less than 0.5 Watt. The results are also studied, and a more precise model of delay time difference is proposed.
KeywordsAdder CMOS gate array maximum time difference wave pipeline
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