Abstract
A Linear Feedback Shift Register (LFSR) can be used to compress test response data as a Signature Analyzer (SA). Parallel Signature Analyzers (PSAs) implemented as multiple input LFSRs are faster and require less hard ware overhead than Serial Signature Analyzers (SSAs) for compacting test response data for Built-In Self-Test (BIST) in IC or board-testing environments. However, the SAs are prone to aliasing errors because of some specific types of error patterns. An alias is a faulty output signature that is identical to the fault-free signature. A penetrating analysis of detecting capability of SAs depends strongly on mathematical manipulations, instead of being aware of some special cases or examples. In addition, the analysis should not be restricted to a particular structure of LFSR, but be appropriate for various structures of LFSRs. This paper presents necessary and sufficient conditions for aliasing errors based on a complete mathematical description of various types of Sas. An LFSR reconfiguration scheme is suggested which will prevent any allasing double errors. Such a prevention cannot be obtained by any extension of an LFSR.
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Min, Y., Malaiya, Y.K. & Jin, B. Aliasing errors in Parallel Signature Analyzers. J. of Comput. Sci. & Technol. 5, 24–40 (1990). https://doi.org/10.1007/BF02946561
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DOI: https://doi.org/10.1007/BF02946561