Abstract
Delay consideration has been a major issue in design and test of high performance digital circuits. The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus, a new delay model is desirable. This paper explores the necessity first. Then, Boolean process to analytically describe the logical and timing behavior of a digital circuit is reviewed. The concept of sensitization is redefined precisely in this paper. Based on the new concept of sensitization, an analytical delay model is introduced. As a result, many untestable delay faults under the logical delay model can be tested if the output waveforms can be sampled at more time points. The longest sensitizable path length is computed for circuit design and delay test.
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Supported by the National Natural Science Foundation of China under the grant No. 69733010.
MIN Yinghua is a Professor of computer science at the Institute of Computing Technology (ICT), Chinese Academy of Sciences and the graduate school, Chinese University of Science and Technology, a guest professor at Hunan University, and Chair of Technical Committee on Faulttolerant Computing, Chinese Computer Federation (CCF). He graduated from Mathematics Department, Jilin University in 1962, and visited some US universities for years. His research interests include IC design and test, fault-tolerant computing, software reliability. He is a fellow of IEEE, and a member of ACM.
LI Zhongcheng is a Professor at the Institute of Computing Technology, Chines Academy of Sciences and the graduate school, Chinese University of Science and Technology. He is the Vice Chair and secretary general of Technical Committee on Fault-Tolerant Computing, CCF. He received his B.S. degree in 1983 from Peking University, M.S. degree in 1986 from ICT and Ph.D. degree in 1991 from ICT. His research interests include IC design and test, software engineering, and reliability.
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Min, Y., Li, Z. An analytical delay model. J. Comput. Sci. & Technol. 14, 97–115 (1999). https://doi.org/10.1007/BF02946516
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DOI: https://doi.org/10.1007/BF02946516