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Automatic circuit extractor for HDL description using program slicing

  • Tun LiEmail author
  • Yang Guo
  • Si-Kun Li
Article

Abstract

Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation, automatic test pattern generation (ATPG). etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain achaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain; it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach.

Keywords

program slicing chaining slice process dependence graph circuit extraction VLSI functional verification 

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Copyright information

© Science Press, Beijing China and Allerton Press Inc., Beijing China and Allerton Press Inc. 2004

Authors and Affiliations

  1. 1.School of Computer Science and TechnologyNational University of Defense TechnologyChangshaP.R. China

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