Abstract
Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Trace Software Pipelining, targeted to the instruction-level parallel processors such as Very Long Instruction Word (VLIW) and superscalar machines. Trace software pipelining applies a global code scheduling technique to compact the original loop body. The resulting loop is called a trace software pipelined (TSP) code. The trace softwrae pipelined code can be directly executed with special architectural support or can be transformed into a globally software pipelined loop for the current VLIW and superscalar processors. Thus, exploiting parallelism across all iterations of a loop can be completed through compacting the original loop body with any global code scheduling technique. This makes our new technique very promising in practical compilers. Finally, we also present the preliminary experimental results to support our new approach.
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References
Fisher J A. Trace scheduling: A technique for global microcode compaction.IEEE Trans. on Computers, 1981, C-30(7).
Rau B R, Fisher J A. Instruction-level parallel processing: History, overview and perspective.The Journal of Supercomputing, 1993, 7(1).
Rau B R, Glaeser C D. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. InProc. of the 14th International Symposium on Microprogramming and Microarchitectures (MICRO-14), Oct. 1981, pp.183–198.
Aiken A, Nicolau A. A Realistic Resource-Constrainted Software Pipelining Algorithm. InLanguage and Compilers for Parallel Computing, Nicolau T Gross A, Gelernter D, Padua D (Eds.), Pitman/The MIT Press, London, 1991, pp.274–290.
Ebcioglu K, Nakatani T. A New Compilation Technique for Parallelizing Loops with Unpredictable Branches on a VLIW Architecture. InLanguage and Compilers for Parallel Computing, Nicolau T Gross A, Gelernter D, Padua D (Eds.), Pitman/The MIT Press, London, 1989, pp.213–229.
Lam M S. A systolic Array optimizing compiler. Ph.D. thesis, CMU, 1987, CMU-CS-87-187.
Su Bogong, Wang Jian. GURPR*: A new global software pipelining algorithm. InProc. of the 24th International Symposium and Workshop on Microprogramming and Microarchitecture (MICRO-24) ACM and IEEE, Nov. 1991, pp.212–216.
Warter N J, Bockhous J W, Haab G E, Subramanian K. Enhanced modulo scheduling for loops with conditional branches. InProc. of the 25th International Symposium on Microprogramming and Microarchitecture (MICRO-25), Dec. 1992.
Wang Jian, Christine Eisenbeis, Jourdan Martin, Su Bogong. Decomposed software pipelining: A new perspective and a new approach.International Journal of Parallel Programming, 1994, 22(3): 357–379.
Luo Yuhua, Li Sanli. A software pipelining algorithm for loop optimization in a RISC architecture.Chinese Journal of Computers, 1993, 16(9). (in Chinese)
Wang Jian, Christine Eisenbeis, Su Bogong. Using timed Petri net to model instruction-level loop scheduling with resource constraints.Journal of Computer Science and Technology, 1994, 9(2): 128–143.
Wang Jian, Andreas Krall, Ertl M Anton. Trace software pipelining. Technique Report TR-1851/94/, Institut für Computersprachen, TU Wien, Austria, 1994.
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This work was supported by the Lise Meitner Stipendium funded by the Austrian Science Foundation (FWF) and the Austrian Science and Research Ministry.
Wang Jian obtained his B.S., M.S. and Ph.D. degrees in computer science in 1986, 1988 and 1991, respectively, all from Tsinghua University. He had worked as a postdoctoral research scientist in INRIA (Paris, France) from Feb. 1992 to Sept. 1993, and in Technical University of Vienna (Austria) from Oct. 1993 to Apr. 1995. He is currently a research associate in McGill University (Montreal, Canada). Dr. Wang has published 40 papers in journals or proceedings of international conferences. His research interests include computer architectures, optimizing compilers, parallel processing, instruction-level parallelism, VLIW/superscalar processors.
Andreas Krall obtained his Dipl.-Ing. degree at Technische UniversitM-dt Wien, Austria in 1983 and his Ph.D. degree in 1988. From 1983 he is an Assistent Professor and from 1995 and Associate Professor at Technische UniversitM-dt Wien. Dr. Krall has published about 30 papers in journals and conference proceedings. His research interests include compiler back-ends, instruction-level parallelism, computer architecture, interpreters and logic programming.
M. Anton Ertl obtained his Dipl.-Ing. degree at Technische UniversitM-dt Wien, Austria in 1991. After one year in the industry, he returned to Technische UniversitM-dt Wien as research and teaching assistant. He is currently pursuing his Ph.D. and hopes to catch it in autumn 1995. Dipl-Ing. Ertl has published 15 papers in journals and conference proceedings. His research interests include compiler back-ends, instruction-level parallelism, computer architecture, stack-based languages, interpreters and constraint logic programming.
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Wang, J., Krall, A. & Ertl, M.A. Trace software pipelining. J. of Comput. Sci. & Technol. 10, 481–490 (1995). https://doi.org/10.1007/BF02943507
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DOI: https://doi.org/10.1007/BF02943507