Abstract
Critical path tracing, a fault simulation method for gate-level combinational circuits, is extended to the parallel critical path tracing for functional block-level combinational circuits. If the word length of the host computer ism, then the parallel critical path tracing will be approximatelym times faster than the original one.
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References
H. Fujiwara, Logic Testing and Design for Testability, Chap. 3, The MIT Press, 1985.
M. Abramovici, P.R. Menon, and D.T. Miller, Critical Path Tracing: An Alternative to Fault Simulation,IEEE Design and Test of Computers, Feb. 1984, 83–93.
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Wei Daozheng, Parallel Critical Path Tracing—A Fault Simulation Algorithm for Combinational Circuits,Chinese Journal of Computers,11:7 (1988), 408–415.
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The project is supported by the National Natural Science Foundation of China.
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Wei, D. Parallel critical path tracing—A fault simulation algorithm for combinational circuits. J. of Compt. Sci. & Technol. 5, 156–163 (1990). https://doi.org/10.1007/BF02943421
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DOI: https://doi.org/10.1007/BF02943421