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A reliable and fault-tolerant interconnection network

  • Deng Yaping 
  • Chen Tinghuai 
Regular Papers

Abstract

An interconnection network with multistage redundant paths is introduced for using in high-performance multiprocessor systems. The routing algorithm of the proposed network is simple and dynamically reroutable. The analysis of the fault-tolerance and performance of the network are given. It is shown that the probability of acceptance and the performance-to-cost ratio of the network are better than those of F and Gamma Networks. Another advantages of the proposed network is the smaller amount of interstage links compared with F network.

Keywords

Interconnection Network Single Fault Switching Element Multistage Interconnection Network Crossbar Switch 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [1]
    D.H. Lawrie, Access and alignment of data in an array processor,IEEE Trans. Comp., C-24:12 (1975), 1145–1155.MATHCrossRefMathSciNetGoogle Scholar
  2. [2]
    C.L.Wu and T.Y. Feng, Routing Techniques for a Class of Multistage Interconnection Networks, Proc. Intl. Conf. on Parallel Processing, Aug. 1978, 197–205.Google Scholar
  3. [3]
    M.C. Pease, The indirect binaryn-cube microprocessor array,IEEE Trans. Comp., C-26:5 (1977), 458–473.MATHCrossRefGoogle Scholar
  4. [4]
    J.H. Patel, Performance of processor-memory interconnection for multiprocessors,IEEE Trans. Comp., C-30:10 (1981), 771–780.CrossRefGoogle Scholar
  5. [5]
    J.E. Lilienkampet al., A Fault Tolerant Interconnection Network Using Error Correcting Codes, Proc. 1982 Intl. Conf. on Parallel Processing, Aug. 1982, 123–125.Google Scholar
  6. [6]
    G.B. Adams III and H.J. Siegel, The extra stage cube: a fault-tolerant interconnection network for supersystems,IEEE Trans. Comp., C-31:5 (1982), 443–454.MATHCrossRefGoogle Scholar
  7. [7]
    K. Padmanaban and D.H. Lawrie, A Fault-Tolerance Scheme in Suffle-Exchange Type Interconnection Networks, Proc. 1983 Intl. Conf. on Parallel Processing, Aug. 1983, 71–75.Google Scholar
  8. [8]
    D.S. Parker and C.S. Reghavendra, The Gamma network,IEEE Trans. Comp., C-33:4 (1984), 367–373.MATHCrossRefGoogle Scholar
  9. [9]
    L. Ciminiera and A. Serra, A connecting network with fault tolerance capabilities,IEEE Trans. Comp., C-35:6 (1986), 578–580.CrossRefGoogle Scholar
  10. [10]
    R.J. McMillen and H.J. Siegel, Routing Schemes for the augmented data manipulator network in an MIMD system.IEEE Trans. Comp., C-31:12 (1982), 1202–1214.MATHCrossRefGoogle Scholar
  11. [11]
    C.P. Kruskal and M. Snir, The performance of multistage interconnection networks for multiprocessor,IEEE Trans. Comp., C-32:8 (1983), 10–18.Google Scholar

Copyright information

© Science Press, Beijing China and Allerton Press Inc. 1990

Authors and Affiliations

  • Deng Yaping 
    • 1
  • Chen Tinghuai 
    • 2
  1. 1.Chongqing Institute of Posts and TelecommunicationsChongqingChina
  2. 2.Chongqing UniversityChongqingChina

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