The design and implementation of a very fast experimental pipelining computer

  • Lin Qi 
  • Xia Peisu 
Regular Papers


The high speed potential of I.C. components can be exploited by shortening the pipeline clock period. Although there are some factors which dominate the shortening, the design of an experimental computer employs the principle of maximum time difference at the system level to determine the clock period and the integrated consideration of architecture, logic design and engineering layout to achieve a system clock period of 9.8 ns using conventional ECL chips of 2ns gate delay. The multiplier in this model, which is constructed with 0.7 ns gate delay chips, can work at a clock period of 5.5 ns.


Propagation Delay Clock Period Logic Design Gate Delay Single Board Computer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Science Press, Beijing China and Allerton Press Inc. 1988

Authors and Affiliations

  • Lin Qi 
    • 1
  • Xia Peisu 
    • 1
  1. 1.Institute of Computing TechnologyAcademia SinicaBeijingChina

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