Abstract
Test Generation for large circuits may be extremely difficult. One of the approaches to alleviating this problem is to consider the difficulties during the design cycle. This paper proposes a design of Easy Test Generation Programmable Logic Arrays (ETG PLAs), for which test generation is basically not required, since a complete test set can be generated while the test is applied. This paper also presents a procedure which makes a PLA an ETG PLA by following some design rules and providing reasonable extra hardware.
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Min, Y. Easy test generation PLAs. J. of Comput. Sci. & Technol. 2, 72–80 (1987). https://doi.org/10.1007/BF02943319
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DOI: https://doi.org/10.1007/BF02943319