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Journal of Computer Science and Technology

, Volume 2, Issue 1, pp 72–80 | Cite as

Easy test generation PLAs

  • Min Yinghua 
Article
  • 14 Downloads

Abstract

Test Generation for large circuits may be extremely difficult. One of the approaches to alleviating this problem is to consider the difficulties during the design cycle. This paper proposes a design of Easy Test Generation Programmable Logic Arrays (ETG PLAs), for which test generation is basically not required, since a complete test set can be generated while the test is applied. This paper also presents a procedure which makes a PLA an ETG PLA by following some design rules and providing reasonable extra hardware.

Keywords

Product Line Test Generation Relational Group Multiple Fault Output Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Science Press, Beijing China and Allerton Press Inc. 1987

Authors and Affiliations

  • Min Yinghua 
    • 1
  1. 1.Chinese Academy of Railway SciencesBeijingChina

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