Journal of Computer Science and Technology

, Volume 2, Issue 1, pp 72–80 | Cite as

Easy test generation PLAs

  • Min Yinghua 


Test Generation for large circuits may be extremely difficult. One of the approaches to alleviating this problem is to consider the difficulties during the design cycle. This paper proposes a design of Easy Test Generation Programmable Logic Arrays (ETG PLAs), for which test generation is basically not required, since a complete test set can be generated while the test is applied. This paper also presents a procedure which makes a PLA an ETG PLA by following some design rules and providing reasonable extra hardware.


Product Line Test Generation Relational Group Multiple Fault Output Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    T.W. William and K.P. Parken, Design for testability—a Survey,IEEE Trans. on Comp. C-31: 1 (1982).CrossRefGoogle Scholar
  2. [2]
    M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Computer Science Press, MD, 1976.Google Scholar
  3. [3]
    D.L. Ostapko and S.J. Hong, Fault analysis and test generation for programmable logic arrays,IEEE Trans. on Comp., C-28:9(1979).CrossRefMathSciNetGoogle Scholar
  4. [4]
    J.E. Smith, Detection of faults in programmable logic arrays,IEEE Trans. on Comp.,C-28:11(1979).Google Scholar
  5. [5]
    V.K. Agarwal, Multiple fault detection in programmable logic arrays,IEEE Trans. on Comp., C-29:6(1980).Google Scholar
  6. [6]
    F.B. Eichelberger and E. Lindbloom, A heuristic test pattern generation for programmable logic arrays,IBM J. Res. and Dev.,24:1,(1980).Google Scholar
  7. [7]
    P. Bose and J.A. Abrahafm, Test generation for programmable logic arrays,19th Design Auto. Conf. Proc., las Vegas, Nevada, 1982, 574–580.Google Scholar
  8. [8]
    J. Khakbaz and E.J. McCluskey, Concurrent error detection and testing for large PLAs,IEEE Trans. on Elec. Devices, ED-29:4(1982).Google Scholar
  9. [9]
    S.L. Wang and A. Avizienis, The design of totally self-checking circuits using programmable logic arrays,Dig. FTCS-9, Wisconsin, 1979.Google Scholar
  10. [10]
    H. Fujiwara and K. Kinoshita, A design of programmable logic arrays with universal tests,IEEE Trans. on Comp. C-30:1(1981).Google Scholar
  11. [12]
    K. Son and D.K. Pradhan, Design of programmable logic arrays for testability,Dig. 1980 Test Conf., PA, 1980.Google Scholar
  12. [13]
    K.S. Ramanatha and N.N. Biswas, A design for testability of undetectable crosspoint faults in programmable logic arrays,IEEE Trans. on Comp. C-32:6(1983).Google Scholar
  13. [14]
    Min Yinghua, Test generation for PLAs,J. of Computers,9:2(1986) (in Chinese).Google Scholar
  14. [15]
    Min Yinghua, A fault model for PLAs,J. of Computers,9:1(1986) (in Chinese).Google Scholar
  15. [16]
    Min Yinghua, A PLA design for ease of test generation,the 14th Int'l conf. on FTC, FL, 1984 436–442.Google Scholar
  16. [17]
    S. Bozorgui-Nesbat and E.J. McCluskey, Lower overthead design for testability of PLAs,Int'l Test Conf., PA, 1984, 856–865.Google Scholar

Copyright information

© Science Press, Beijing China and Allerton Press Inc. 1987

Authors and Affiliations

  • Min Yinghua 
    • 1
  1. 1.Chinese Academy of Railway SciencesBeijingChina

Personalised recommendations