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A built-in test pattern generator

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Abstract

Built-in testing is currently of more concern due to the difficulties in testing a VLSI by using an external tester. In addition, Built-In Testing is also necessary for on-line testing and a fault-tolerant computing system. Using a Linear Feedback Shift Register (LFSR) as a built-in test pattern generator (BITPG) is a realistic and simple approach. An LFSR with maximum length can generate pseudo-random test patterns or all non-null vectors for exhaustive testing. This paper presents an LFSR design with non-maximum length to serve as a BITPG to generate a given test setT, which efficiently saves testing time. A search-verification process for designing this kind of LFSR is employed and implemented by the program SVBITPG. This paper presents the diagram of the program and gives some examples to illustrate the design of the BITPG.

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Authors and Affiliations

  1. Chinese Academy of Railway Sciences, Beijing, China

    Min Yinghua

  2. Northern Jiaotong University, Beijing, China

    Han Zhide

Authors
  1. Min Yinghua
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  2. Han Zhide
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Min, Y., Han, Z. A built-in test pattern generator. J. of Compt. Sci. & Technol. 1, 62–74 (1986). https://doi.org/10.1007/BF02943309

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  • DOI: https://doi.org/10.1007/BF02943309

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