Design of a vector processor

  • Lin Qi 


This paper discusses the inherent parallelism limits on several applications for vector computers, the parallel capabilities of several architectures and two ways (traditional instruction control flow and data control flow) by which the capabilities can be used. Then a scheme for a pipelined vector processor of multi-processing units is presented. The basic system structure and its function on highly sparse vector processing are described. A vector cache system and a distributed main memory are also considered, which are intended to sustain extremely high access rates for the processor. A microprocessor based vector processor is constructed, which can simulate the high performance version of the processor.


Current Vector Array Processor Access Rate Vector Computer Sparse Vector 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. [1]
    I.S. Duff and J.K. Reid, Experience of Sparse Matrix Codes on the CRAY-1,Computer Physics Communications,26 (1982).Google Scholar
  2. [2]
    CDC CYBER 200 Model 205 Computer System Hardware Reference Manual, Control Data Corporation, 1981.Google Scholar
  3. [3]
    CRAY-1 Computer System Reference Manual, Cray Research Inc., Minneapolis, 1976.Google Scholar
  4. [4]
    Alan Jay Smith, Cache Memories,Computer Surveys,14:3(1982), 473–530.CrossRefGoogle Scholar
  5. [5]
    The CRAY X-MP Series, Publication No. MP-0001, Cray Research Inc., 1982.Google Scholar

Copyright information

© Science Press, Beijing China and Allerton Press Inc. 1986

Authors and Affiliations

  • Lin Qi 
    • 1
  1. 1.Institute of Computing TechnologyAcademia SinicaBeijingChina

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