Abstract
This paper describes the partitioning of the set of the Boolean equations generated by the hardware logic translator and the conversion of the subsets into cube arrays. Subsequent to this, it is aimed: (1) to find out the minimal sets of input variables; (2) to finish the logic minimization; and (3) to decompose a large logic array into smaller ones to meet the design constraints if necessary.
These three problems can all be reduced to solving the corresponding covering problems, which may have considerable scales. This paper gives the method to solve large cycling cover tables of these problems with cover-matrix complementation (sharp operation). The salient feature of the method is that it can give the optimal solutions and need not store the covering matrix.
The above work is intended to set up an automatic logic synthesis system to translate register transfer level language descriptions into hardware logic diagrams.
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Liu, M., Hong, E. Some covering problems and their solutions in automatic logic synthesis systems. J. of Compt. Sci. & Technol. 1, 83–92 (1986). https://doi.org/10.1007/BF02943275
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DOI: https://doi.org/10.1007/BF02943275