Abstract
At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transition-graph of the proposed BIST scheme are analyzed. Based on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.
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This work was supported by the National Natural Science Foundation of China under grant Nos.69976002 and 69733010.
This work was completed when the author was in Peking University, China.
LI Xiaowei received his B.Eng. and M.Eng. degrees in computer science from Hefei University of Technology, China in 1985 and 1988, respectively. He received his Ph.D. degree in computer science from the Institute of Computing Technology, The Chinese Academy of Sciences in 1991. Dr. Li joined Peking University, China as a postdoctoral research fellow and a lecturer in 1991, and was promoted to associate professor in 1993, all with the Department of Computer Science and Technology. He was a Visiting Research Fellow in the Department of Electrical and Electronic Engineering at the University of Hong Kong from 1997–1998. He was a Visiting Professor in the Graduate School of Information Science, Nara Institute of Science and Technology, Japan in 1999. At present, he is a professor in the Institute of Computing Technology, The Chinese Academy of Sciences. His research interests include VLSI testing, design for testability, built-in self-test, high-level synthesis for testability, software testing and hardware/software co-test.
Paul Y.S. Cheung received his B.S. (Eng) degree with first-class honour in 1973 and his Ph.D. degree in 1978, both in EE from the Imperial College of Science and Technology, University of London. After working for Queen’s University of Belfast for two years as an engineer-in-charge of a laboratory, he returned to Hong Kong in 1978 to take up an academic position at the Hong Kong Polytechnic University. He joined the University of Hong Kong as a lecturer in 1980 and was promoted to senior lecturer/associate professor in 1987. He served as the Associate Dean of Faculty of Engineering from 1991–1994 and has been the Dean of Faculty of Engineering at the University of Hong Kong since 1994. He was the Director of IEEE Asia Pacific in 1995–1996 and served as the secretary of IEEE in 1997. His research interests include parallel computer architecture, Internet computing, VLSI design and testing, signal processing and pattern recognition.
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Li, X., Paul Y. S., C. A loop-based apparatus for at-speed self-testing. J. Comput. Sci. & Technol. 16, 278–285 (2001). https://doi.org/10.1007/BF02943206
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DOI: https://doi.org/10.1007/BF02943206