Fault-tolerant design techniques in A CMP architecture
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Single-chip multiprocessor (CMP) combined with the fault-tolerant (FT) techniques offers an ideal architecture to achieve high availability on the basis of sustaining high computing performance. FT design of a single-chip multiprocessor is described, including the techniques from hardware redundancy to software support and firmware strategy. The design aims at masking the influences of errors and automatically correcting the system states.
Key wordscomputer architecture fault-tolerant design single-chip multiprocesor
CLC numberTP 311
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