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Fault-tolerant design techniques in A CMP architecture

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Wuhan University Journal of Natural Sciences

Abstract

Single-chip multiprocessor (CMP) combined with the fault-tolerant (FT) techniques offers an ideal architecture to achieve high availability on the basis of sustaining high computing performance. FT design of a single-chip multiprocessor is described, including the techniques from hardware redundancy to software support and firmware strategy. The design aims at masking the influences of errors and automatically correcting the system states.

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Authors and Affiliations

  1. Department of Computer Science and Technology, Tsinghua University, 10084, Beijing, China

    Yao Wen-bin

  2. Research Institute of Information Technology, Tsinghua University, 10084, Beijing, China

    Yao Wen-bin & Wang Dong-sheng

Authors
  1. Yao Wen-bin
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  2. Wang Dong-sheng
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Additional information

Foundation item: Supported by the National High Technology Development 863 Program of China(2002AA1Z030) and China Postdoctoral Science Foundation(2003034151)

Biography: YAO Wen-bin (1972-), male, Postdoctor, research direction: fault-tolerant computing and computer architecture.

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Wen-bin, Y., Dong-sheng, W. Fault-tolerant design techniques in A CMP architecture. Wuhan Univ. J. Nat. Sci. 10, 5–8 (2005). https://doi.org/10.1007/BF02828605

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  • DOI: https://doi.org/10.1007/BF02828605

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