Journal of Electronics (China)

, Volume 12, Issue 2, pp 151–159 | Cite as

On shortening test sequence length for signature analyzer

  • Ding Jin
  • Hu Jiandong


Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature. Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.

Key words

Built-in self-test Worst fault Signature analysis Probability optimization 


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  1. [1]
    H. J. Wunderlich, PROTEST: A tool for probabilistic testability analysis. Proc. of the 22nd Design Automation Conference, Las Vegas-Nevada: 1985, 204–211.Google Scholar
  2. [2]
    A. R. Virupakshia, V. C. Reddy,IEEE Trans. on C,C-32 (1983) 6, 594–597.MATHCrossRefGoogle Scholar
  3. [3]
    H. J. Wunderlich, On computing optimized input probabilities for random tests. Proc. of the IEEE 24th Design Automation Conference, Washington: 1987, 392–398.Google Scholar
  4. [4]
    J. R. Humphrey, K. Firooz, Signature analysis for board testing.The Radio and Electronic Engineer, (1981) 1, 37–50.Google Scholar
  5. [5]
    M. R. Sudhakap, K. Kewal,IEEE Trans. on C,37 (1988) 9, 1151–1156.CrossRefGoogle Scholar
  6. [6]
    S. K. Jain, V. D. Agrawal, STAFAN: An alternative to fault simulation. Proc. of the 21st Design Automation Conference, Albuquerque: 1984, 18–23.Google Scholar
  7. [7]
    S. C. Seth, V. D. Agrawal, PREDICT: Probabilistic estimation of digital circuit testability. Proc. of the 15th International Symposium on Fault-tolerant Computing, Michigan: 1985, 220–225.Google Scholar
  8. [8]
    S. C. Seth et al., An exact analysis for efficient computation of random-pattern testability in combination circuits. Proc. of the 16th International Fault-tolerant Computing Symposium, Washington: 1986, 318–323.Google Scholar
  9. [9]
    B. Krishnamurthy, I. G. Tools,IEEE Trans. on C,C-38 (1989) 7, 1041–1045.CrossRefGoogle Scholar
  10. [10]
    Ding Jin, Hu Jiandong, On the eliminating of parameters α and β in STAFAN. Proc. of the 2nd Asian Test Symposium, Beijing: 1993, 72–74.Google Scholar
  11. [11]
    J. Savir et al.,IEEE Trans. on C,C-33 (1984) 1, 79–90.MATHCrossRefGoogle Scholar
  12. [12]
    J. Savir, P. H. Bardell,IEEE Trans. on C,C-33 (1984) 6, 467–474.MATHCrossRefGoogle Scholar
  13. [13]
    C. K. Chin, E. J. McCluskey,IEEE Trans. on C,C-36 (1987) 2, 252–256.CrossRefGoogle Scholar
  14. [14]
    M. S. Bershtein,Kibernetica, (1979) 4, 53–56, (in Russian).Google Scholar

Copyright information

© Science Press 1995

Authors and Affiliations

  • Ding Jin
    • 1
  • Hu Jiandong
    • 1
  1. 1.Beijing University of Posts and TelecommunicationsBeijing

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