Novel deprocessing technique for failure analysis of flip-chip integrated circuit packages

Abstract

A novel technique for flip-chip package deprocessing that allows for detailed failure analysis of internal flip-chip packaging structures and chip circuitry has been developed. A systematic approach of selective wet etching and plasma etching is utilized. Understanding of package level reliability can be greatly enhanced with the capability to systematically access and examine defects in three-dimensions with powerful analytical tools such as the SEM/EDS. Additionally, the ability to inspect large areas of internal packaging structures, e.g., solder bump array, in three-dimensions makes it faster and more convenient to locate defects, compared to two-dimensional techniques such as progressive cross-sectioning. Case studies involving defects in solder bumps, underfill material, and substrate metallization are presented.