Securing the AES Cryptographic Circuit Against Both Power and Fault Attacks

  • Jinbao Zhang
  • Ning WuEmail author
  • Fang Zhou
  • Fen Ge
  • Xiaoqiang Zhang
Original Article


Aiming to protect cryptographic circuits against physical attacks, researchers have proposed a variety of mature and effective countermeasures. However, most of these defensive technologies are used for specific and single attack, thus it is hard to thwart combined attack, such as combined power and fault attacks. In this paper, we propose a dual complementary infection countermeasure for Advanced Encryption Standard (AES) cryptographic circuit to defend against both power and fault attacks. According to the target AES circuit, we first design and construct a dual complementary AES circuit to defend against power attacks, which can balance the power consumption when processing different data. Besides, to defend against fault attacks, in the dual complementary AES circuit, we design an improved random infection mechanism to diffuse the effect of injected faults. Experiment results show that the proposed countermeasure can thwart both power and fault attacks effectively. Compared with those AES circuits which can only defend against single attack, our designed circuit increases greatly the security under extra 83.1% area overhead and 2.1% impacts on the maximum working frequency.


AES Fault attacks Differential power attack Countermeasures 



This work was supported by National Natural Science Foundation of China under Grant (No. 61774086), the Fundamental Research Funds for Central Universities (Nos. NP2019102, NS2016041), and the Natural Science Foundation of Jiangsu Province (No. BK20160806).


  1. 1.
    Weiwei S, Xingyuan F, Zhipeng X (2015) A secure reconfigurable crypto IC with countermeasures against SPA, DPA, and EMA. IEEE Trans Comput Aid Des Integr Circ Syst 34(7):1201–1205CrossRefGoogle Scholar
  2. 2.
    Saeed A, Ahmadinia A, Just M (2016) Secure on-chip communication architecture for reconfigurable multi-core systems. J Circ Syst Comput 25(8):1181–1192CrossRefGoogle Scholar
  3. 3.
    Daemen J, Rijmen V (2002) The design of Rijndael: AES, the advanced encryption standard. Springer, BerlinCrossRefzbMATHGoogle Scholar
  4. 4.
    Karaklajić D, Schmidt JM, Verbauwhede I (2013) Hardware designer’s guide to fault attacks. IEEE Trans Very Large Scale Integr Syst 21(12):2295–2306CrossRefGoogle Scholar
  5. 5.
    Kocher PC, Jaffe J, Jun B (1999) Differential power analysis. In: Wiener MJ (ed) Advances in cryptology - CRYPTO ’99, 19th Annual international cryptology conference, Santa Barbara, California, USA, 15–19 August 1999. Lecture notes in computer science, vol 1666. Springer, Berlin, Heidelberg, pp 388–397Google Scholar
  6. 6.
    Piret G, Quisquater JJ (2003) A differential fault attack technique against SPN structures, with application to the AES and Khazad. In: Walter CD, Koç ÇK, Paar C (eds) Workshop on cryptographic hardware and embedded systems (CHES) 2003, Cologne, Germany, 8–10 September 2003. Lecture notes in computer science, vol 2779. Springer, Berlin, Heidelberg, pp 77–88Google Scholar
  7. 7.
    Dassance F, Venelli A (2012) Combined fault and side-channel attacks on the AES key schedule. In: Workshop on fault diagnosis and tolerance in cryptography (FDTC) 2012, Leuven, Belgium, 9 September 2012. IEEE Computer Society, pp 63–71Google Scholar
  8. 8.
    Clavier C, Feix B, Gagnerot G, Roussellet M (2010) Passive and active combined attacks on AES— combining fault attacks and side channel analysis. In: Workshop on fault diagnosis and tolerance in cryptography (FDTC) 2010, Santa Barbara, California, USA, 21 August 2010. IEEE Computer Society, pp 10–19Google Scholar
  9. 9.
    Roche T, Lomné V, Khalfallah K (2011) Combined fault and side-channel attack on protected implementations of AES. In: Prouff E (ed) Smart card research and advanced applications - 10th IFIP WG 8.8/11.2 International conference, CARDIS 2011, Leuven, Belgium, 14–16 September 2011. Lecture notes in computer science, vol 7079. Springer, Berlin, Heidelberg, pp 65–83Google Scholar
  10. 10.
    Tiri K, Verbauwhede I (2004) A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: 2004 Design, automation and test in Europe conference and exposition (DATE 2004), Paris, France, 16–20 February 2004. IEEE Computer Society, pp 246–251Google Scholar
  11. 11.
    Ye Y, Wu N, Zhang X, Dong L, Zhou F (2018) An optimized design for compact masked AES S-box based on composite field and common subexpression elimination algorithm. J Circuits Syst Comput 27(11):1850171CrossRefGoogle Scholar
  12. 12.
    Bilgin B, Gierlichs B, Nikova S, Nikov V, Rijmen V (2014) A more efficient AES threshold implementation. In: Pointcheval D, Vergnaud D (eds) Progress in cryptology - AFRICACRYPT 2014. Lecture notes in computer science, vol 8469. Springer, Cham, pp 267–284CrossRefGoogle Scholar
  13. 13.
    Bilgin B, Gierlichs B, Nikova S, Nikov V, Rijmen V (2015) Trade-offs for threshold implementations illustrated on AES. IEEE Trans Comput Aid Des Integr Circ Syst 34(7):1188–1200CrossRefzbMATHGoogle Scholar
  14. 14.
    Mestiri H, Kahri F, Bouallegue B, Machhout M (2016) A high-speed AES design resistant to fault injection attacks. Microprocess Microsyst 41:47–55CrossRefGoogle Scholar
  15. 15.
    Guo X, Karri R (2013) “Recomputing with permuted operands: a concurrent error detection approach”, IEEE Trans. Comput Aid Des Integr Circ Syst 32(10):1595–1608CrossRefGoogle Scholar
  16. 16.
    Barenghi A, Breveglieri L, Koren I, Naccache D (2012) Fault injection attacks on cryptographic devices: theory, practice, and countermeasures. Proc IEEE 100(11):3056–3076CrossRefGoogle Scholar
  17. 17.
    Tupsamudre H, Bisht S, Mukhopadhyay D (2014) Destroying fault invariant with randomization. A countermeasure for AES against differential fault attacks. In: Batina L, Robshaw M (eds) Workshop on cryptographic hardware and embedded systems (CHES) 2014, Busan, South Korea, 23–26 September 2014. Lecture notes in computer science, vol 8731. Springer, Berlin, Heidelberg, pp 93–111Google Scholar
  18. 18.
    Lomne V, Roche T, Thillard A (2012) On the need of randomness in fault attack countermeasures - application to AES. In: Workshop fault diagnosis tolerance cryptography (FDTC) 2012, Leuven, Belgium, 9 September 2012. IEEE Computer Society, pp 85–94Google Scholar
  19. 19.
    Zhao J, Han J, Zeng X, Li L, Deng Y (2008) Differential power analysis and differential fault attack resistant AES algorithm and its VLSI implementation. In: 9th International conference on solid-state and integrated-circuit technology (ICSICT). IEEE, pp 2220–2223Google Scholar
  20. 20.
    Schneider T, Moradi A, Güneysu T (2016) ParTI – towards combined hardware countermeasures against side-channel and fault-injection attacks. Advances in cryptology – CRYPTO 2016. Lecture notes in computer science, vol 9815. Springer, Berlin, Heidelberg, pp 302–332CrossRefGoogle Scholar
  21. 21.
    Cnudde TD, Nikova S (2017) Securing the PRESENT block cipher against combined side-channel analysis and fault attacks. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(12):3291–3301CrossRefGoogle Scholar
  22. 22.
    Mangard S, Oswald E, Popp T (2010) Power analysis attacks: revealing the secrets of smart cards. Springer, BerlinzbMATHGoogle Scholar
  23. 23.
    Zhang X, Parhi KK (2004) High-speed VLSI architectures for the AES algorithm. IEEE Trans Very Large Scale Integr (VLSI) Syst 12(9):957–967CrossRefGoogle Scholar
  24. 24.
    Canright D (2005) A very compact S-box for AES. In: Rao JR, Sunar B (eds) Workshop on cryptographic hardware and embedded systems (CHES) 2005, Edinburgh, UK, 29 August–1 September 2005. Lecture notes in computer science, vol 3659. Springer, Berlin, Heidelberg, pp 441–455Google Scholar
  25. 25.
    Zhang J, Wu N, Zhang X, Zhou F (2016) Against fault attacks based on random infection mechanism. IEICE Electron Express 13:1–6Google Scholar
  26. 26.
    Wang B, Liu L, Deng C, Zhu M, Yin S, Wei S (2016) Against double fault attacks: injection effort model, space and time randomization based countermeasures for reconfigurable array architecture. IEEE Trans Inf Forensics Secur 11(6):1151–1164CrossRefGoogle Scholar
  27. 27.
    Fournier J, Rigaud JB, Bouquet S, Robisson B, Tria A, Dutertre JM, Agoyan M (2011) Design and characterisation of an AES chip embedding countermeasures. Int J Intell Eng Inf 1(34):328–347Google Scholar
  28. 28.
    Derbez P, Fouque PA, Leresteux D (2011) Meet-in-the-middle and impossible differential fault analysis on AES. Workshop on cryptographic hardware and embedded systems (CHES) 2011, Nara, Japan, 28 September–1 October 2011. Lecture notes in computer science, vol 6917. Springer, Berlin, Heidelberg, pp 274–291Google Scholar

Copyright information

© The Korean Institute of Electrical Engineers 2019

Authors and Affiliations

  • Jinbao Zhang
    • 1
  • Ning Wu
    • 1
    Email author
  • Fang Zhou
    • 1
  • Fen Ge
    • 1
  • Xiaoqiang Zhang
    • 2
  1. 1.College of Electronic and Information EngineeringNanjing University of Aeronautics and AstronauticsNanjingChina
  2. 2.College of Electrical EngineeringAnhui Polytechnic UniversityWuhuChina

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