# Selective harmonic elimination (SHE) based 3-phase multilevel voltage source inverter (VSI) for standalone applications

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## Abstract

The breakthroughs in power electronics semiconductor technology have led to the raised in popularity of Multi-level Voltage Source Inverters, which is the reason industries and researchers are relentlessly working towards extending it to both medium and high-power applications. Consequently, this paper presents a modified Selective Harmonic Elimination Pulse Width Modulation (SHE-PWM) controlled three-phase 5-level Multi-level Inverter (MLI) topology. The work is an extension of a single-phase topology proposed by the authors. The uniqueness of the proposed topology is that it comprises of six Cascaded H-bridge modules (two modules per phase) that are powered through a single direct current (DC) source, hence eliminating the need for multiple DC sources. In addition, conventional 5-level MLI has two switching angles (n = 2), which restricts its harmonic elimination capability to one (n = 1) lower order harmonics. This study removes that restriction by utilising the concept of multiple switching per step, resulting in the superimposing of 12 notches (n = 12) on the output voltage at the 3/9 distribution ratio. With the fundamental switching SHE-PWM, twelve non-linear, transcendental equations are generated, and they are optimally solved using the Hybrid Coded Genetic Algorithm to eliminate 11 (n − 1) lower-order harmonics. The low-switching frequency results in less electromagnetic interference as well as reduced switching loss, which improves the overall inverter efficiency. The topology has less output Total Harmonics Distortion, fewer components, and lower weight and cost than conventional topologies. The circuit was designed and validated through simulations performed in PSIM software.

## Keywords

Total harmonic distortion (THD) Selective harmonic elimination (SHE) Reduced device count Multi-level inverter## 1 Introduction

The advent of enhanced power electronic devices coupled with the demand for clean, sustainable and friendly energy sources, has resulted in a rapid research surge in renewable energy conversion technology. The ability of a Multilevel inverter (MLI) to concatenate smaller voltages to attain the required high voltage value has been the reason for its recent prominence and dominance in the field of energy conversion [1, 2, 3]. In the ordinary conventional two-level inverter, the output total harmonic distortion (THD) is reduced by increasing the inverter switching frequency, which is at the detriment of the switching losses. Unlike the two-level, the MLI medium voltage step reduces voltage stress on the power switches. Its low switching frequency makes it generate less electromagnetic interference (EMI), and its modular nature simplifies its control strategy and provides easy maintenance and the possibility of incorporating redundancy along with fault tolerance operation [3, 4].

The commonly known MLI topologies are broadly classified into Diode Clamped (DiC) [5], Flying Capacitor (FC) [6] and Cascaded H-bridge (CHB) with multiple DC sources [7]. They are popularly referred to as conventional converters because they form the basic building block of almost all the modified and hybrid topologies. MLI converters utilise low power switches to generate any required output voltage level, making them suitable for medium and high power applications. Each topology has its own merits and demerits. For instance, DiC has an unequal voltage sharing problem across the switches and its number of clamping diodes increases with output levels [8], while the FC output level increases with an increase in the number of capacitors. This results in a need for an additional feedback control mechanism that monitors and regulates the capacitor voltage level, which further complicates and increases the bulkiness of the system. Its high frequency of operation results in higher switching losses which deteriorate the inverter efficiency [5]. In the case of CHB topology, similar to the FC, the output level increases with more H-bridge modules and independent DC sources [7].

Quite a number of researchers have developed various MLI topologies to address the issue of the increased number of H-bridge modules and multiple DC sources in CHB converters. However, unfortunately, most of them ended up making the circuit bulky and complicating the control strategy, which results in reduced efficiency and increased output THD in the system [9, 10, 11].

A new converter topology was proposed by Kang et al. [12] to realise higher voltage step with a reduced number of power electronic switches [12]. The author uses three H-bridge modules along with a specially designed transformer having three primary windings and cascaded secondary with multiple turns ratio of 1:1, 1:1 and 1:3, respectively. Two of the h-bridge modules were controlled at fundamental frequency to synthesize the output component, while the third module is run at a slightly higher frequency to generate a series of notches that compensate for the voltage level step transition, therefore minimizing the harmonic output content [7]. The topology was able to increase the voltage output steps and reduced the THD level. The drawbacks are the transformer size that is attributed to the low frequency and turns ratio as well as the poor THD quality it exhibits at light load since output harmonics were only suppressed not wholly eliminated. In a similar work published in [13], the same circuit configuration was used but with a different transformer turns ratio and PWM control function. The frequency of operation was increased, which results in a reduction of the physical transformer size and turns ratio by the scale of half (1:0.5). The drawback is that the switching frequency increases which affects the power electronic switch lifespan and results in high switching losses. Rao et al. [14] proposed a new topology that incorporates additional DC sources and switches to achieve higher voltage steps (m) [14]. For an “m” number of steps, the topology requires m + 3 power electronic switches per phase, which is a 50% switch reduction in the conventional CHB and FC topologies. The drawback of the topology is the need for additional DC sources, sophisticated control circuity, high switching and uneven voltage distribution across the power switches. Gobinath et al. [15] developed a three-phase reduced switch MLI topology that is capable of generating seven levels using seven power switches and three DC sources per phase. Another positive feature of this topology is its ability to operate in three modes, namely powering, freewheeling and regenerative modes. Its drawbacks are similar to that of the previous, i.e. increased DC sources, complex control circuitry and uneven voltage distribution across the power electronic switches [15].

In an effort to proffer the solution to a similar problem, this study develops a five-level three-phase reduced switch MLI topology, which is controlled by using multiple notches (3/9) per step and SHE-PWM. A conventional five-level MLI has two voltage steps per quarter, which is equivalent to two (n = 2) switching angles per quarter. Based on the SHE-PWM theorem, for ‘n’ switching per quarter, ‘n − 1’ harmonics will be eliminated. Hence, for ‘n = 2’ only one lower order harmonics is eliminated. Therefore, introducing multiple switching per quarter increases the MLI ability to eliminate lower order harmonics, which eliminates the need to increase the output step. In view of this, the hybrid coded genetic algorithm optimization technique reported in [16] is used to solve the switching angles that eliminate the 11 (n − 1) lower order harmonics optimally. This idea is implemented in the single-phase topology published in [1]. The topology contains two H-bridges connected in parallel with a single DC source. Each of the module terminals is connected to the primary side of a cascaded secondary side transformer having a 1:1 turns ratio. The SHE-PWM fundamental switching reduces the output THD while at the same time, it maintains a better efficiency due to switching loss reduction. This study extends the same topology to three-phase applications. It comprises six H-bridges that are all powered through a single DC source, with transformers connected at each module terminal to prevent short-circuits within the power switches as well as load isolation. In a three-phase system, even and triplen harmonics cancel each other out in the output; therefore, only the 11 odd non-triplen harmonics are targeted for elimination. The switching angles are the same as those used in the single-phase [1] with subsequent phases shifted by 120º and 240°, respectively.

## 2 Converter topology

This section explains the inverter topology modes of operation, how the switching angles were obtained, and the switching function used to realise the 5-level voltage waveform.

### 2.1 The proposed 3-phase converter topology and its circuit operations

_{xyt}, where ‘x’ represents the module number within a phase, which could be either 1 or 2. Whereas ‘y’ stand for the switch number within a module and is between 1 and 4. The subscript ‘t’ denotes the switch phase and are represented by alphabet a, b and c. With appropriate switching function, the inverter generates stable five and nine voltage steps in the phase and line respectively. The concepts of multiple notches per steps enable the topology to eliminate ten extra harmonics than the usual conventional one. Moreover, it has cut down the number of DC sources from six to one, which has a significant impact on the inverter size, weight, cost and complexity.

Switching combinations

Voltage | Switching states | |||||||
---|---|---|---|---|---|---|---|---|

S | S | S | S | S | S | S | S | |

0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |

+ E | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |

+ E | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |

0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |

− E | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 |

− E | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |

+ 2E | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |

− 2E | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |

### 2.2 Mathematical modelling of the proposed 3-phase topology

*α*1

*to α*12) per quarter cycle. It is assumed that it obeys both half and quarter-wave symmetry theorem. The top waveform represents the inverter phase voltage, which is the summation of the phase H-bridge modules terminal voltages

*V*1 and

*V*2. Based on the terminal voltage

*V*1, it appears the majority of the notches are generated by module 1, signifying that module 1 power switches are subjected to more switching stress than that of module 2. Module 2 produces terminal voltage

*V*2, which is used for power transfer to the load side. Hence, making it switches to experience high conduction losses. However, this research is not aimed at ensuring equal power distribution and losses within the inverter modules and its power switches.

*n*= 12) switching angles per quarter wave with 3/9 distribution ratio. Therefore, based on SHE-PWM theorem, eleven (

*n*− 1) lower-order dominant harmonics will be eliminated. Equation (1) is the Fourier Series expansion used to model the output waveform mathematically, leading to the generation of twelve non-linear transcendental equations. The equations comprise of a fundamental component and eleven lower-order harmonics. Since we are dealing a three-phase system, it means only the first eleven odd non-triplen harmonics are of concerned to us, i.e. (5th, 7th, 11th, 13th, 17th, 19th, 23rd, 25th, 29th, 31st, 35th) [1, 19, 20].

Due to both half and quarter-wave symmetry of the output waveform, 1/4th representing 0–90 range of the waveform is enough to model the entire waveform.

*π*, l =

*π*. The general expression for the co-efficient of the sinusoidal output component obtained using Eq. (3) is given by Eq. (4):

*Pn*and

*Pm*represent the number of the switching angles per distribution ratio and ranges from 1–3 to 4–12, respectively, and K is an integer representing the switching angle number. Thus, substituting them reduces the expression to:

## 3 Results and discussion

This section presents the optimized switching angle solutions, the simulated output voltage waveforms along with it Fast Fourier Transforms FFT, conventional topologies component device comparison, the THD and efficiency comparison of the proposed and conventional CHB topology.

### 3.1 Switching angle solutions

Optimized switching angles

s/n | Phase A | Phase B | Phase C |
---|---|---|---|

1 | 13.40246 | 133.40246 | 253.40246 |

2 | 15.67567 | 135.67567 | 255.67567 |

3 | 19.61681 | 139.61681 | 259.61681 |

4 | 35.50001 | 155.50001 | 275.50001 |

5 | 37.80673 | 157.80673 | 277.80673 |

6 | 46.26136 | 166.26136 | 286.26136 |

7 | 48.24797 | 168.24797 | 288.24797 |

8 | 54.85481 | 174.85481 | 294.85481 |

9 | 58.37752 | 178.37752 | 298.37752 |

10 | 61.01313 | 181.01313 | 301.01313 |

11 | 83.87128 | 203.87128 | 323.87128 |

12 | 86.01930 | 206.0193 | 326.0193 |

### 3.2 Simulation results

*V*1 and

*V*2 for Phase A, while Fig. 5 depicts their corresponding gating signals with switch

*S*11

*a*to

*S*14

*a*controlling module 1 and

*S*21

*a*to

*S*24

*a*for module 2. Both terminal voltages and switching signals correspond with the sketch made during the design procedure. The two voltages

*V*1 and

*V*2 add up to produce the required five level waveforms with 3/9 switching distribution ratio. Moreover, the gating signals satisfies the inverter switching combination provided in Table 1. In the same manner, the other terminal voltages and gating signals for Phase B and Phase C were generated with 120 and 240° out of phase with Phase A.

### 3.3 Topologies device counts comparison

Components comparison between conventional 9-level Multi-level inverter topologies and the proposed

Topology type | No of switches | Dc-Bus |
---|---|---|

Diode-clamp (DiC) [5] | 6(K − 1) | (K − 1) |

Flying capacitor (FC) [6] | 6(K − 1) | (K − 1) |

Cascaded H-bridge (CHB) [7] | 6(K − 1) | 0.5(K − 1) |

New MLI with reduced count (NMLTRC) [21] | 12 + 1.5(K − 1) | 1.5(K − 1) |

New MLI with self-balancing level (NMLISBL) [22] | 3(K + 1) | 0.5(3K + 1) |

Novel MLI with minimum switch number (NMLIMSN) [23] | 12 + 1.5(K − 3) | 0.5(K − 1) + 3 |

Proposed topology | 6(K − 5) | 1 |

### 3.4 Comparison between conventional and proposed topology

## 4 Conclusion

The objective of this research is to develop an inverter with less output harmonics and reduced device count. Therefore, a 3-phase five-level MLI output waveform was realized using a single Dc source and a modified cascaded H-bridge topology. The inverter was controlled using selective harmonic elimination technique where the non-linear transcendental equations were solved using an optimized genetic algorithm to obtain the switching angles. The harmonic contents obtained over a range of output power satisfies the IEEE standards. The number of power electronic switches and the DC source for the proposed topology was compared against six other topologies, where it turns out to have the least number of components. Efficiency and THD of the proposed topology were compared against a conventional 3-phase H-bridge having the same number of output level. The proposed appeared to have better efficiency and has the least output harmonic distortions. Therefore, it can be concluded that the control strategy and the proposed topology are suitable for fixed frequency applications standalone applications. For future recommendations, fault-tolerant control can be employed on the topology to exploit its modularity and redundant switching. In addition, different optimizers and modulation techniques can be used on the topology to assess its performance. Different transformer turns ratio as well as switching angle distribution can be used to increase the inverter output steps and harmonic eliminations capabilities.

## Notes

### Acknowledgements

The authors gratefully acknowledge the financial support from Universiti Malaysia Pahang Grant, RDU1703226.

### Compliance with ethical standards

### Conflict of interest

The authors declare that they have no conflict of interest.

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