An energy-efficient RAM cell based on novel majority gate in QCA technology
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The limitations of the Complementary Metal–Oxide–Semiconductor (CMOS) technology such as the dissipated power, hard lithography, and short channel effects, led the researchers to look for an alternative technology. The unique properties of the QCA technology such as low dissipated power, speed, and the small feature size were the reason for considering it as a CMOS alternative in this work. In this paper, a new layout for five input single layer majority gate is proposed. The proposed majority gate is used in order to carry out new low power RAM cell with the ability to set the output or to reset it. Designing a cost efficient memory cell is an important issue because it is a brick unit for the whole RAM that considers the most essential component in the digital system. The proposed RAM cell shows improvement around 7% in terms of cost function and a noticeable reduction in switching energy. The QCADesigner tool is used in this work for circuit design and verification while the QCAPro tool is used for power analysis.
KeywordsQuantum-dot cellular automata RAM cell Majority gate QCA memory
CMOS-based devices face lots of challenges including short-channel effects, hard lithography and significant increase in power dissipation . QCA is one of the most important nanotechnologies presented as a possible alternative to CMOS-based devices [2, 3]. The idea of QCA was first noted in 1993 by Lent et al. . QCA was implemented physically by four techniques: magnetic, metal island, molecular and semiconductor  and recently many papers discussed new implementation developments [5, 6]. The basic blocks in QCA are an inverter and majority voter. Many papers introduced this technique for designing a new structure of the majority gate. Design of an optimal structure of majority gate leads to improvements in the QCA circuit’s performance. Other techniques were suggested to optimize QCA circuits such as [7, 8, 9, 10]. Memory design attracted researchers’ interest, especially in QCA. As in VLSI, QCA has many parameters for evaluation of the circuit performance such as delay, power dissipation, and area. The reliability of QCA circuits is also important and need to be considered carefully . This research proposed a new structure of majority voter with five inputs and utilized it to design a new low power RAM cell structure. An analysis of power dissipation is also provided. The proposed design has many aspects such as lower power consumption, minimum area, single layer implementation. In addition, the inputs are placed outside the design and crosstalk is avoided which makes the gate more extendable and robust.
In this paper, QCA fundamentals are reviewed in Sect. 2, five bits majority gate are discussed in Sect. 3, QCA memory cell mechanisms have been presented in Sect. 4, the related works are provided in Sect. 5, the proposed designs are introduced in Sect. 6, Sect. 7 shows the simulation results with comparison tables, finally, the conclusion will be presented in Sect. 8.
2 QCA fundamentals
4 RAM cell
5 Related work
6 The proposed designs
Many important circuits carried out in QCA technology utilized Maj-5 as a building blocks such as an adder circuit, parity generator, and RAM cell. RAM cell was implemented in QCA following many schematic circuits, most of them utilized three-inputs majority gate (Maj-3) and five-inputs majority gate (Maj-5) in order to reduce the circuit complexity. In the proposed design, the proposed Maj-5 will be utilized as a building block in order to carry out the optimal layout QCA-RAM cell because current loop-based RAM cells are not sufficiently optimized .
Functionality table of the proposed RAM cell
Output (t − 1)
7 Simulation results and comparisons
Characteristics of many previous designs of 5-inputs majority gates
The power consumption analysis for different Maj-5 gates
Maj-5 presented in
Avg. leakage energy dissipation (meV)
Avg. switching energy dissipation (meV)
Total energy consumption (meV)
Overall the results indicate that the proposed circuits have many features: lower cell counts, lower cost, lower latency, and lower power consumption as a primary circuit in digital systems.
A new layout single layer majority-5 gate is presented. The majority gate is utilized to carry out a new QCA-RAM cell with the ability to set or reset the output. QCADesigner tool is utilized in this work for circuit design and verification while QCAPro tool is used for power analysis. The advantages of the proposed designs are a small area, low dissipated power, low cost, and low complexity. The proposed circuits are done in a single layer which make them more realistic for physical implementation.
Compliance with ethical standards
Conflict of interest
On behalf of all authors, the corresponding author states that there is no conflict of interest.
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