# An energy-efficient RAM cell based on novel majority gate in QCA technology

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## Abstract

The limitations of the Complementary Metal–Oxide–Semiconductor (CMOS) technology such as the dissipated power, hard lithography, and short channel effects, led the researchers to look for an alternative technology. The unique properties of the QCA technology such as low dissipated power, speed, and the small feature size were the reason for considering it as a CMOS alternative in this work. In this paper, a new layout for five input single layer majority gate is proposed. The proposed majority gate is used in order to carry out new low power RAM cell with the ability to set the output or to reset it. Designing a cost efficient memory cell is an important issue because it is a brick unit for the whole RAM that considers the most essential component in the digital system. The proposed RAM cell shows improvement around 7% in terms of cost function and a noticeable reduction in switching energy. The QCADesigner tool is used in this work for circuit design and verification while the QCAPro tool is used for power analysis.

## Keywords

Quantum-dot cellular automata RAM cell Majority gate QCA memory## 1 Introduction

CMOS-based devices face lots of challenges including short-channel effects, hard lithography and significant increase in power dissipation [1]. QCA is one of the most important nanotechnologies presented as a possible alternative to CMOS-based devices [2, 3]. The idea of QCA was first noted in 1993 by Lent et al. [4]. QCA was implemented physically by four techniques: magnetic, metal island, molecular and semiconductor [1] and recently many papers discussed new implementation developments [5, 6]. The basic blocks in QCA are an inverter and majority voter. Many papers introduced this technique for designing a new structure of the majority gate. Design of an optimal structure of majority gate leads to improvements in the QCA circuit’s performance. Other techniques were suggested to optimize QCA circuits such as [7, 8, 9, 10]. Memory design attracted researchers’ interest, especially in QCA. As in VLSI, QCA has many parameters for evaluation of the circuit performance such as delay, power dissipation, and area. The reliability of QCA circuits is also important and need to be considered carefully [11]. This research proposed a new structure of majority voter with five inputs and utilized it to design a new low power RAM cell structure. An analysis of power dissipation is also provided. The proposed design has many aspects such as lower power consumption, minimum area, single layer implementation. In addition, the inputs are placed outside the design and crosstalk is avoided which makes the gate more extendable and robust.

In this paper, QCA fundamentals are reviewed in Sect. 2, five bits majority gate are discussed in Sect. 3, QCA memory cell mechanisms have been presented in Sect. 4, the related works are provided in Sect. 5, the proposed designs are introduced in Sect. 6, Sect. 7 shows the simulation results with comparison tables, finally, the conclusion will be presented in Sect. 8.

## 2 QCA fundamentals

## 3 Majority-5

## 4 RAM cell

## 5 Related work

## 6 The proposed designs

Many important circuits carried out in QCA technology utilized Maj-5 as a building blocks such as an adder circuit, parity generator, and RAM cell. RAM cell was implemented in QCA following many schematic circuits, most of them utilized three-inputs majority gate (Maj-3) and five-inputs majority gate (Maj-5) in order to reduce the circuit complexity. In the proposed design, the proposed Maj-5 will be utilized as a building block in order to carry out the optimal layout QCA-RAM cell because current loop-based RAM cells are not sufficiently optimized [23].

^{\}. When the set and reset lines connected to different logical values which are ‘0’ and ‘1’, the selection line is enabled and if the Write/Read

^{\}line is setting to ‘1’, write operation will be activated, the input value will appear at the output, In addition, the read operation is done by connecting the Write/Read

^{\}line to ‘0’. If Set and Reset lines are connected to the same logic value ‘1’, set mode enabled and the output will go high (logic ‘1’). Similarly, reset mode enabled if the Set and Reset lines are connected to logic ‘0’ then the output will be reset to ‘0’.

Functionality table of the proposed RAM cell

Operation | W/R | Select | Set | Reset | Output (t) |
---|---|---|---|---|---|

Read | 0 | 1 | 0 | 1 | Output (t − 1) |

Write | 1 | 1 | 0 | 1 | Input |

Set | X | X | 1 | 1 | 1 |

Reset | X | X | 0 | 0 | 0 |

## 7 Simulation results and comparisons

Characteristics of many previous designs of 5-inputs majority gates

The power consumption analysis for different Maj-5 gates

Maj-5 presented in | Avg. leakage energy dissipation (meV) | Avg. switching energy dissipation (meV) | Total energy consumption (meV) | ||||||
---|---|---|---|---|---|---|---|---|---|

0.5 Ek | 1 Ek | 1.5 Ek | 0.5 Ek | 1 Ek | 1.5 Ek | 0.5 Ek | 1 Ek | 1.5 Ek | |

Ref. [27] | 3.44 | 10.67 | 19.52 | 32.66 | 29.89 | 27.01 | 36.1 | 40.56 | 46.53 |

Ref. [15] | 1.28 | 4.14 | 7.69 | 11.53 | 10.37 | 9.16 | 12.81 | 14.51 | 16.85 |

Ref. [16] | 3.38 | 8.95 | 15.03 | 9.23 | 7.7 | 6.41 | 12.61 | 16.65 | 21.44 |

Ref. [17] | 1.35 | 4.25 | 7.8 | 10.94 | 9.84 | 8.7 | 12.29 | 14.09 | 16.5 |

Proposed | 3.67 | 9.42 | 15.57 | 5.77 | 4.71 | 3.86 | 9.43 | 14.13 | 19.42 |

_{k}, 1 E

_{k}, and 1.5 E

_{k}) at a temperature of 2 k. According to the results taken from QCAPro tool, the proposed design wastes less energy than previous similar designs. The results show that the memory cell proposed in this work leads to improvements of approximately 60%, 6% and 40% in terms of switching, leakage and total energy dissipation relative to previous similar circuits.

_{k}. In this form, dark cells represent high energy dissipation. It is clear that the proper configuration of cells in the proposed majority voter made it less energy dissipation compared to current memory cells.

Overall the results indicate that the proposed circuits have many features: lower cell counts, lower cost, lower latency, and lower power consumption as a primary circuit in digital systems.

## 8 Conclusions

A new layout single layer majority-5 gate is presented. The majority gate is utilized to carry out a new QCA-RAM cell with the ability to set or reset the output. QCADesigner tool is utilized in this work for circuit design and verification while QCAPro tool is used for power analysis. The advantages of the proposed designs are a small area, low dissipated power, low cost, and low complexity. The proposed circuits are done in a single layer which make them more realistic for physical implementation.

## Notes

### Compliance with ethical standards

### Conflict of interest

On behalf of all authors, the corresponding author states that there is no conflict of interest.

## References

- 1.Khosroshahy MB, Moaiyeri MH, Navi K, Bagherzadeh N (2017) An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata. Results Phys 7:3543–3551CrossRefGoogle Scholar
- 2.Goswami M, Sen B, Mukherjee R, Sikdar BK (2017) Design of testable adder in quantum-dot cellular automata with fault secure logic. Microelectron J 60:1–12CrossRefGoogle Scholar
- 3.Bruschi F, Perini F, Rana V, Sciuto D (2011) An efficient quantum-dot cellular automata adder. In: 2011 design, automation & test in Europe, pp 1–4Google Scholar
- 4.Lent CS et al (1993) Quantum cellular automata. Nanotechnology 4:49–57CrossRefGoogle Scholar
- 5.Gonelli M, Fin S, Carlotti G, Dey H, Csaba G, Porod W et al (2018) Robustness of majority gates based on nanomagnet logic. J Magn Magn Mater 460:432–437CrossRefGoogle Scholar
- 6.Khosroshahy MB, Daliri MS, Abdoli A, Navi K, Bagherzadeh N (2016) A 3D universal structure based on molecular-QCA and CNT technologies. J Mol Struct 1119:86–95CrossRefGoogle Scholar
- 7.Khosroshahy MB, Moaiyeri MH, Angizi S, Bagherzadeh N, Navi K (2017) Quantum-dot cellular automata circuits with reduced external fixed inputs. Microprocess Microsyst 50:154–163CrossRefGoogle Scholar
- 8.Alkaldy E, Majeed AH, Bin Zainal MS, Bin Md Nor D (2020) Optimum multiplexer design in quantum-dot cellular automata. Indones J Electr Eng Comput Sci 17:148–155Google Scholar
- 9.Majeed AH, Alkaldy E, Bin Zainal MS, Bin Md Nor D (2019) Synchronous counter design using novel level sensitive T-FF in QCA technology. J Low Power Electron Appl 9:27CrossRefGoogle Scholar
- 10.Sayedsalehi S, Moaiyeri M, Navi K (2013) Design of efficient and testable n-input logic gates in quantum-dot cellular automata. J Comput Theor Nanosci 10(10):2347–2353CrossRefGoogle Scholar
- 11.Alkaldy E, Navi K (2013) Reliability study of single stage multi-input majority function for QCA. Int J Comput Appl 83:2Google Scholar
- 12.Angizi S, Sarmadi S, Sayedsalehi S, Navi K (2015) Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata. Microelectron J 46:43–51CrossRefGoogle Scholar
- 13.Angizi S, Alkaldy E, Bagherzadeh N, Navi K (2014) Novel robust single layer wire crossing approach for exclusive or sum of products logic design with quantum-dot cellular automata. J Low Power Electron 10:259–271CrossRefGoogle Scholar
- 14.Lent CS, Tougaw PD (1997) A device architecture for computing with quantum dots. Proc IEEE 85:541–557CrossRefGoogle Scholar
- 15.Navi K, Farazkish R, Sayedsalehi S, Rahimi Azghadi M (2010) A new quantum-dot cellular automata full-adder. Microelectron J 41:820–826CrossRefGoogle Scholar
- 16.Roohi A, Khademolhosseini H, Sayedsalehi S, Navi K (2014) A symmetric quantum-dot cellular automata design for 5-input majority gate. J Comput Electron 13:701–708CrossRefGoogle Scholar
- 17.Navi SSK, Farazkish R, Azghadi MR (2010) Five input majority gate, a new device for quantum-dot cellular automata. J Comput Theor Nanosci 7:1546–1553CrossRefGoogle Scholar
- 18.Majeed AH, AlKaldy E, Zainal MSB, Nor DBMD (2019) A new 5-input majority gate without adjacent inputs crosstalk effect in QCA technology. Indones J Electr Eng Comput Sci 14:1159–1164CrossRefGoogle Scholar
- 19.Navi K, Farazkish R (2012) New efficient five-input majority gate for quantum-dot cellular automata. J Nanopart Res 14:1252CrossRefGoogle Scholar
- 20.Farazkish R, Khodaparast F (2015) Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata. Microprocess Microsyst 39:426–433CrossRefGoogle Scholar
- 21.Walus K, Vetteth A, Jullien GA, Dimitrov VS (2003) RAM design using quantum-dot cellular automata. In: Proceedings of nanotechnology conference and trade show, vol 2, pp 160–163Google Scholar
- 22.Moghimizadeh T, Mosleh M (2019) A novel design of fault-tolerant RAM cell in quantum-dot cellular automata with physical verification. J Supercomput 75:5688–5716CrossRefGoogle Scholar
- 23.Dehkordi MA, Shamsabadi AS, Ghahfarokhi BS, Vafaei A (2011) Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata. Microelectron J 42:701–708CrossRefGoogle Scholar
- 24.Navi K, Sayedsalehi S, Farazkish R, Rahimi Azghadi M (2010) Five input majority gate, a new device for quantum-dot cellular automata. J Comput Theor Nanosci 7:1546–1553CrossRefGoogle Scholar
- 25.Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J 43:929–940CrossRefGoogle Scholar
- 26.Bagherian Khosroshahy M, Moaiyeri M, Navi K (2017) Design and evaluation of a 5-input majority gate-based content-addressable memory cell in quantum-dot cellular automata. 19th international symposium on computer architecture and digital systemsGoogle Scholar
- 27.Akeela R, Wagh MD (2011) A five input majority gate in quantum dot cellular automata. NanoTech 2:978–981Google Scholar
- 28.Liu W, Lu L, O’Neill M, Swartzlander EE (2014) A first step toward cost functions for quantum-dot cellular automata designs. IEEE Trans Nanotechnol 13:476–487CrossRefGoogle Scholar
- 29.Azimi S, Angizi S, Moaiyeri M (2018) Efficient and robust SRAM cell design based on quantum-dot cellular automata. ECS J Solid State Sci Technol 7:Q38–Q45CrossRefGoogle Scholar