Regression based FPGA power estimation tool (FPE_Tool) for embedded multiplier block
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Latest FPGA devices integrate processor, DSP blocks and memories as IP cores, due to which it is possible to build high performance FPGA based embedded applications. As all these hard and soft IP blocks are integrated on a single FPGA chip, the system consumes more power, which grows up at each new generation. Inside FPGA, embedded multiplier block is extensively used in the high performance design applications. Early estimation of power for this block provide evaluation to designer to design high performance and low power applications. In this paper a power estimation model has been developed for embedded multiplier block targeted to Spartan 3 FPGAs. The model is developed using regression and curve fitting approach. Several configurations of embedded multiplier having different I/O vector length are instantiated using Core Generator Tool and Xilinx Xpower Analyzer is used to compute leakage power and dynamic power.
KeywordsChip enable Slice Look up table Statistical model Power estimation
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