A high time resolution and low-power ASIC for MRPC applications
The structure of readout circuits needs to be improved to meet the requirements of the endcap time of flight upgrade with multi-gap resistive plate chamber (MRPC) in Beijing Spectrometer III experiments, posing a demand for the high time resolution and low-power electronics.
Considering MRPC features, an application-specific integrated circuit (ASIC) called FEEWAVE, which integrates the front-end circuit and digitization function, is proposed to meet the above requirements. The front-end circuit implements I/V conversion and signal amplification. To reduce power consumption and further improve the time resolution, the waveform sampling technique based on switch capacitor array is adopted.
Results and conclusion
A 30 fC to 1.2 pC input signal dynamic range is obtained, and the jitter is less than 21 ps rms. At the same time, the chip realizes 5 GSPS (gigabit samples per second) sampling rate, trigger rate capability of 50 kHz and 25 mW/channel power consumption. The 6-channel ASIC has been designed and taped out with 0.18 \(\upmu \)m complementary metal oxide semiconductor technology. The preliminary test results of FEEWAVE have been achieved.
KeywordsMRPC Waveform sampling ASIC
The waveform sampling part mentioned in this work was improved from its first version, which was implemented in the JUNO collaboration by IHEP, Tsinghua University and University of Science and Technology of China. We acknowledge Prof. Fukun Tang in the University of Chicago for his strong guidance and advice on the previous SCA chip. This work was supported by a Grant from the National Natural Science Foundation of China (No. 11505205).
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