Design and offline processing of an ultrafast digitizer based on internal cascaded DRS4

  • Ya-Fei DuEmail author
  • Jun Wu
  • Chen Yuan
  • Bo Yang
  • Cen-Ming Ye
  • Chuan-Fei Zhang
  • Yi-Nong Liu


In this paper, we present an ultrafast digitizer utilizing the DRS4 switched capacitor array application-specific integrated circuit to achieve an ultrafast sampling speed of at most 5 GS/s. We cascaded all eight channels (sub-channels) of a single DRS4 chip for increased storage depth. The digitizer contains four DRS4 chips, a quad-channel analog-to-digital converter, a controlling field-programmable gate array, a PXI interface, and an SFP+ connector. Consequently, each DRS4 channel has a depth of 8192 points and a vertical resolution of 14 bits. The readout sequences should be broken into several segments and then reordered to obtain the correct sequential data sets, and this offline procedure varies in different readout modes. This paper describes the design and implementation of the hardware; in particular, the respective processing procedures are described in detail. Furthermore, the offset error is calibrated and corrected to improve the precision of the captured waveform in both single-channel and high-resolution modes.


Ultrafast Digitizer DRS4 Cascade Readout 


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Copyright information

© China Science Publishing & Media Ltd. (Science Press), Shanghai Institute of Applied Physics, the Chinese Academy of Sciences, Chinese Nuclear Society and Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Ya-Fei Du
    • 1
    • 2
    Email author
  • Jun Wu
    • 2
  • Chen Yuan
    • 2
  • Bo Yang
    • 2
  • Cen-Ming Ye
    • 2
  • Chuan-Fei Zhang
    • 2
  • Yi-Nong Liu
    • 1
  1. 1.Department of Engineering PhysicsTsinghua UniversityBeijingChina
  2. 2.Institute of Nuclear Physics and Chemistry, China Academy of Engineering PhysicsMianyangChina

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