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High-Speed High-Throughput VLSI Architecture for RSA Montgomery Modular Multiplication with Efficient Format Conversion

  • Aashish PariharEmail author
  • Sangeeta Nakhate
Original Contribution

Abstract

Modular multiplication is a key operation in RSA cryptosystems. Modular multipliers can be realized using Montgomery algorithm. Montgomery algorithm employing carry save adders makes modular multiplication suitable and efficient. Montgomery modular multiplication can be carried out in two ways. All the operands are kept in carry save form in one of the ways. The input and output are kept in binary form, and intermediate operands are kept in carry save form in the other way which requires an efficient format converter. This paper proposes a fast and high-throughput Montgomery modular multiplier which employs an efficient format conversion method. Format conversion is carried out through a format conversion unit which consists of a carry look-ahead unit and multiplexer unit. In addition, this multiplier merges two iterations, which reduces the number of clock cycles significantly. Merger of iteration requires integer multiples of inputs which is computed using the same format converter. Critical path delay of the multiplier is minimized by multiplying one of the inputs by four which simplifies necessary intermediate calculations. The total time required for one complete multiplication is significantly minimized due to reduction in required number of clock cycles with optimum critical path delay. Experimental results show that the proposed multiplier achieves significant speed and throughput improvement as compared to previous designs.

Keywords

Carry save addition VLSI Modular exponentiation Montgomery modular multiplier Rivest, Shamir, and Adleman (RSA) cryptosystem 

Notes

Acknowledgement

Authors are thankful to the project “Special Manpower Development Program for Chip to System Design (SMDP-C2SD)” sponsored by Ministry of Electronics and Information Technology (MeitY), Government of India, for providing technical facility.

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Copyright information

© The Institution of Engineers (India) 2019

Authors and Affiliations

  1. 1.Department of Electronics and CommunicationMaulana Azad National Institute of TechnologyBhopalIndia

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