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A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique

  • Sreenivasulu Polineni
  • M. S. Bhat
  • Arulalan Rajan
Research Article - Electrical Engineering
  • 21 Downloads

Abstract

A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology.

Keywords

SAR ADC Binary-weighted DAC Capacitor Switching technique Input common mode range Switching energy per conversion Energy efficiency Mismatch INL DNL 

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Copyright information

© King Fahd University of Petroleum & Minerals 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of TechnologySurathkalIndia

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