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Benefitting from High-κ Spacer Engineering in Balistic Triple-Gate Junctionless FinFET- a Full Quantum Study

  • Nazanin Baghban Bousari
  • Mohammad K. AnvarifardEmail author
  • Saeed Haji-Nasiri
Original Paper
  • 11 Downloads

Abstract

In this paper, a numerically comprehensive investigation have been performed in order to propose a high-κ spacer triple-gate junctionless FinFET (HKS TG JL FinFET) in three dimensional (3D) simulation domain. In the proposed structure, a high dielectric insulator called as HfO2 is used on the both sides of the source and the drain regions as the spacers. The spacer located on the drain side, extends into the channel region and the other spacer is only on the channel region. Mode Space Non-Equilibrium Green’s Function method has been utilized in order to analyze the nanoscale proposed structure. The modification of the electric field along the channel region is introduced as the main reason for the improvement of the electrical characteristics. Also, the explored results about role of different thicknesses of the proposed structure spacers on the electrical performance are discussed in the last section. The explored results have revealed that the leakage current is successfully reduced about 20% and also Ion/Ioff experiences a 30% increase for the proposed structure. Also, the short channel effects in terms of subthreshod slope and drain induced barrier lowering (DIBL) is improved about 11.59% and 50% respectively. It is stated that the HKS JL TG FinFET can be a good candidate for future high speed applications.

Keywords

Triple-gate Junctionless FinFET High-κ spacer engineering NEGF 

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References

  1. 1.
    Colinge JP (2007) Multi-gate SOI MOSFETs. Elsevier Microelectron Eng 84(6):2071–2076.  https://doi.org/10.1016/j.sse.2003.12.020 CrossRefGoogle Scholar
  2. 2.
    Molaei R, Saremi M (2018) A resonant tunneling nanowire field effect transistor with physical contractions: a negative differential resistance device for low power very large scale integration applications. J Electron Mater 47(2):1091–1098.  https://doi.org/10.1007/s11664-017-5823-z CrossRefGoogle Scholar
  3. 3.
    Hisamoto D, Lee W, Kedzierski J, Takeuchi H, Asano K (2000) FinFET – A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Devices 47(12):2320–2325.  https://doi.org/10.1109/16.887014 CrossRefGoogle Scholar
  4. 4.
    Yu B et al (2002) FinFET scaling to 10 nm gate length. In: IEEE conference publication, pp 251–254.  https://doi.org/10.1109/IEDM.2002.1175825
  5. 5.
    Molaei R, Saremi M, Vandenberghe W (2017) A novel PNPN-like Z-shaped tunnel field- effect transistor with improved ambipolar behavior and RF performance. IEEE Trans Electron Devices 64(11).  https://doi.org/10.1109/TED.2017.2755507 CrossRefGoogle Scholar
  6. 6.
    Saremi M, Afzali-Kusha A, Mohammadi S (2012) Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits. IEEE Trans Electron Devices 64(11).  https://doi.org/10.1016/j.mee.2012.01.009 CrossRefGoogle Scholar
  7. 7.
    Anvarifard M, Orouji A (2018) Enhancement of a nanoscale novel Esaki tunneling diode source TFET (ETDS-TFET) for low-voltage operations. Silicon 1–10.  https://doi.org/10.1007/s12633-018-0043-6
  8. 8.
    Boukortt N, Patanè S, Crupi G (2019) 3D investigation of 8-nm tapered n-FinFET model. Silicon 1–9.  https://doi.org/10.1007/s12633-019-00253-y
  9. 9.
    Saha R, Bhowmick B, Baishya S (2019) Impact of mole fractions due to work function variability (WFV) of metal gate on electrical parameters in strained SOI-FinFET. Silicon 1–7.  https://doi.org/10.1007/s12633-019-00163-z
  10. 10.
    Das R, Goswami R, Baishya S (2016) Tri-gate heterojunction SOI Ge-FinFETs. Superlattice Microst 91:51–61.  https://doi.org/10.1016/j.spmi.2015.12.039 CrossRefGoogle Scholar
  11. 11.
    Priscilla S, Srinivasan R (2018) Optimization of nanometer bulk junctionless trigate FET using gate and isolation dielectric engineering. Mater Sci Semicond Process 84:107–114.  https://doi.org/10.1016/j.mssp.2018.05.009 CrossRefGoogle Scholar
  12. 12.
    Paz B, Cassé M et al (2016) Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectron Reliab 63:1–10.  https://doi.org/10.1016/j.microrel.2016.05.006 CrossRefGoogle Scholar
  13. 13.
    Trevisoli R et al (2012) Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors. IEEE Trans Electron Devices 59(12):3510–3518.  https://doi.org/10.1109/TED.2012.2219055 CrossRefGoogle Scholar
  14. 14.
    Saini G, Choudhary S (2016) Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance. J Comput Electron 15:84–93.  https://doi.org/10.1007/s10825-015-0769-y CrossRefGoogle Scholar
  15. 15.
    Bousari N, Anvarifard M, Haji-Nasiri S (2019) Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering. Int J Electron Commun (AEÜ) 108:226–234.  https://doi.org/10.1016/j.aeue.2019.06.017 CrossRefGoogle Scholar
  16. 16.
    Atamuratov A et al (2017) Simulation of DIBL effect in 25 nm SOIFinFET with the different body shapes. Nanosystems Phys Chem Math 71–74.  https://doi.org/10.17586/222080542017817174
  17. 17.
    Colinge J et al (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225–229.  https://doi.org/10.1038/NNANO.2010.15 CrossRefPubMedGoogle Scholar
  18. 18.
    Baidya A, Baishya S, Lenka T (2017) Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor. Mater Sci Semicond Process 71:413–420.  https://doi.org/10.1016/j.mssp.2017.08.031 CrossRefGoogle Scholar
  19. 19.
    Baruah R, Paily R (2014) A dual-material gate junctionless transistor with high-k spacer for enhanced analog performance. IEEE Trans Electron Devices 61(1):123–128.  https://doi.org/10.1109/TED.2013.2292852 CrossRefGoogle Scholar
  20. 20.
    Akbari M, Anvarifard M (2017) A novel graphene nanoribbon FET with an extra peak electric field (EFP-GNRFET) for enhancing the electrical performances. Phys Lett A 381:1379–1385.  https://doi.org/10.1016/j.physleta.2017.02.032 CrossRefGoogle Scholar
  21. 21.
    Drive P, Clara S (2010) Atlas User’s Manual, device Simulation Software: 1-1715. www.silvaco.com
  22. 22.
    Anantram M, Lundstrom M, Dmitri E, Nikonov D (2008) Modeling of nanoscale devices. Proc IEEE 96(9):1511–1550.  https://doi.org/10.1109/JPROC.2008.927355 CrossRefGoogle Scholar
  23. 23.
    Narendar V, Mishra R (2015) Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs). Superlattice Microst 85:357–369.  https://doi.org/10.1016/j.spmi.2015.06.004 CrossRefGoogle Scholar
  24. 24.
    Selvadurai A (2000) Partial differential equations in mechanics 2. Springer, Berlin, pp 503–647CrossRefGoogle Scholar
  25. 25.
    Shao X, Yu Z (2005) Nanoscale FinFET simulation: A quasi-3D quantum mechanical model using NEGF. Solid State Electron 49(8):1435–1445.  https://doi.org/10.1016/j.sse.2005.04.017 CrossRefGoogle Scholar
  26. 26.
    Datta S (2000) Nanoscale device modeling: the Green’s function method. Superlattice Microst 28(4):253–278.  https://doi.org/10.1006/spmi.2000.0920 CrossRefGoogle Scholar
  27. 27.
    Andrade M et al (2012) Behavior of triple-gate bulk FinFETs with and without DTMOS operation. Solid State Electron 71:63–68.  https://doi.org/10.1016/j.sse.2011.10.022 CrossRefGoogle Scholar
  28. 28.
    Orouji A, Anvarifard M (2013) SOI MOSFET with an insulator region (IR-SOI): a novel device for reliable nanoscale CMOS circuits. Mater Sci Eng B 178(7):431–437.  https://doi.org/10.1016/j.mseb.2013.01.017 CrossRefGoogle Scholar
  29. 29.
    Aminbeidokhti A, Orouji A, Rahmaninezhad S, Ghasemian M (2012) A novel high-breakdown-voltage SOI MESFET by modified charge distribution. IEEE Trans Electron Devices 59(5):1255–1262.  https://doi.org/10.1109/TED.2012.2186580 CrossRefGoogle Scholar

Copyright information

© Springer Nature B.V. 2019

Authors and Affiliations

  1. 1.Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin BranchIslamic Azad UniversityQazvinIran
  2. 2.Department of Engineering Sciences, Faculty of Technology and Engineering, East of GuilanUniversity of GuilanRudsar-VajargahIran

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