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Performance Investigation of Gate Engineered tri-Gate SOI TFETs with Different High-K Dielectric Materials for Low Power Applications

  • P. VimalaEmail author
  • T. S. Arun Samuel
  • M. Karthigai Pandian
Original Paper


In this article, a three-dimensional model of Tri-gate Tunnel Filed effect transistors (TFET) with different gate materials is proposed. Analysis and comparison of various structures such as single material gate, double material gate and triple material gate of a Tri-gate TFET is performed with respect to both DC and AC characteristics. Various electrical parameters that define the performance of a semiconductor device are verified using Silvaco TCAD Simulation results. Parameters analyzed in this work include surface potential, lateral electric field, total electric field along the channel, drain current, transconductance and output conductance of single material, double material and triple material Tri-gate TFETs. The comparative performance analysis shows a better DC and AC performance for Triple Material Tri-gate TFET (TMTGTFET) in comparison to single material and double material Tri-gate devices. It could be inferred that short channel effects are considerably reduced in a gate engineered Tri-Gate TFET structure and it also shows remarkable improvement in ON current as the current increases 45% for TMTGTFET when compared to a SMTG TFET. To improve the TMTGTFET performance, different dielectric materials are employed for device characteristics.


Drain current Single material Double material Triple material Tri-gate TFET TCAD 


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This research work is financially supported by Defense Research and Development Organization (DRDO), Government of India through the grant ERIP/ER/1504753/M/01/1629.


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© Springer Nature B.V. 2019

Authors and Affiliations

  1. 1.Department of ECEDayananda Sagar College of EngineeringBengaluruIndia
  2. 2.Department of ECENational Engineering CollegeKovilpattiIndia
  3. 3.Department of ICESri Krishna College of TechnologyCoimbatoreIndia

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