pp 1–12 | Cite as

Reduction in Self-Heating Effect of SOI MOSFETs by Three Vertical 4H-SiC Layers in the BOX

  • Behrooz Abdi Tahne
  • Ali NaderiEmail author
  • Fatemeh Heirani
Original Paper


In this paper a novel structure is proposed for silicon on insulator MOSFETs which improves DC and RF characteristics by three vertical layers of 4H-SiC. Vertical layers are in parallel and extended from silicon drift region toward the substrate through oxide region as heating passageways. These additional layers absorb the heat of active region and transfer to the substrate area. Thus, large value of temperature variation arising from high gate and drain biasing in SOI devices is reduced by applying the proposed structure. It reduced from ~690 K to ~353 K at VG = 10 V. The negative differential resistance is diminished and carriers mobility improved which result in higher and more stable saturation current in comparison with conventional structure. Also, the resultant device has lower delay time. Gate capacitances are approximately equal to the conventional structure but its higher transconductance results in more than 3-times higher cut-off frequency and about 75% improvement in maximum oscillation frequency, at VG = 10 V and VD = 3.5 V. Widespread simulations and comparisons demonstrate that this structure can be considered in high power and RF applications.


SOI-MOSFET Self heating TVL-SOI Lattice temperature Delay time Mobility 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.



  1. 1.
    Anvarifard MK, Orouji AA (2013) Improvement of self-heating effect in a novel nanoscale SOI MOSFET with undoped region: a comprehensive investigation on DC and AC operations. Superlattice Microst 60:561–579CrossRefGoogle Scholar
  2. 2.
    Zheng XZ, Lin Q, Zhu M, Lin Ch L (2004) A new structure of SOI MOSFET for reducing self-heating effect. Ceram Int 30:1289–1293Google Scholar
  3. 3.
    Chu PK (2005) Novel silicon-on-insulator structures for reduced self-heating effects. IEEE Circ Syst Mag 5:18–23Google Scholar
  4. 4.
    Daghighi A, Zamani S (2010) Investigation of the thermal effects of 45nm silicon on diamond (SOD) transistor. Diam Relat Mater 32:63–68Google Scholar
  5. 5.
    Rahimian M, Orouji AA (2012) A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect. Mater Sci Semicond Process 15:445–454CrossRefGoogle Scholar
  6. 6.
    Rahimian M, Orouji AA (2013) Investigation of the electrical and thermal performance of SOI MOSFETs with Modified Channel engineering. Mater Sci Semicond Process 16:1248–1256CrossRefGoogle Scholar
  7. 7.
    Shahnazarisani H, Mohammadi S (2015) Simulation analysis of a novel fully depleted SOI MOSFET: electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator. Physica E: Low-dimensional Systems and Nanostructures. Physica E 69:13–26Google Scholar
  8. 8.
    Xiaorong L, Bo Z, Zhaoji L (2008) New high-voltage ( 1200 V) MOSFET with the charge trenches on partial SOI. IEEE T Electron Dev 55:1756–1761Google Scholar
  9. 9.
    Park J, Grasser M, Kosina HT et al (2003) A numerical study of partial-SOI LDMOSFETs. Solid State Electron 47:275–281CrossRefGoogle Scholar
  10. 10.
    Hue Y, Huang Q, Wang G, Chang S, Wang H (2012) A novel high-voltage>600 V LDMOSFET with buried N-layer in partial SOI technology. IEEE T Electron Dev 59:1131–1136Google Scholar
  11. 11.
    JamaliMahabadi SE, Rajabi S, Loiaconoa J (2015) A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement. Superlattice Microst 85:872–879CrossRefGoogle Scholar
  12. 12.
    JamaliMahabadi SE, Oruji AA, Keshavarzi p RS, Aminimoghadam H, Iranian pour haghighi M (2011) A novel step buried oxide partial SOI LDMOSFET with triple drift layer.
  13. 13.
    Lou X, Wang YG, Lei T, Fu D, Yao G, Oiao M, Zhang B, Li Z (2011) Novel high voltage LDMOS on partial SOI with double-sided charge trenches.
  14. 14.
    Gammon PM, Al e (2017) Design and fabrication of silicon-on-silicon-carbide substrate and power devices for space applications. E3S Web of Conferences 16:12003Google Scholar
  15. 15.
    Wu Y, Kapolnek D, Ibbetson JP, Parikh P, Keller BP, Mishra UK (2001) Very-high power density AlGaN/GaN HEMTs. IEEE T Electron Dev 48:586–590Google Scholar
  16. 16.
    Gaska R, Osinsky A, Yang JW, Shur Michael S (1998) Self-heating in high-power AlGaN-GaN HFETs. IEEE Electron Device L 19:89–91Google Scholar
  17. 17.
    Santa C (2008) Device simulation software, ATLAS user’s manual, Silvaco International, CAGoogle Scholar
  18. 18.
    Gu B, Liu HY, Mai YW, Feng XQ, Yu SW (2008) Fracture mechanics analysis of the effects of temperature and material mismatch on the smart-cut technology. Eng. Fracture Mech 75:4996–5006CrossRefGoogle Scholar
  19. 19.
    Aminbeidokhti A, Orouji AA, Rahmaninezhad S, Ghasemian M (2012) A novel high-breakdown-voltage SOI MESFET by modified charge distribution. IEEE T Electron Dev 59:1255–1262Google Scholar
  20. 20.
    Anvarifard MK, AA (2015) A novel nanoscale SOI MOSFET with si embedded layer as an effective heat sink. International Journal of Electronics 102:1394–1406CrossRefGoogle Scholar
  21. 21.
    Michaeli W (1992) Extrusion dies for plastics and rubber. 2nd Ed, Hanser publishers, New YorkGoogle Scholar
  22. 22.
    Ramezani Z, Orouji AA (2017) Amended electric field distribution: a reliable technique for electrical performance improvement in nano scale SOI MOSFETs. J Electron Mater 46:2269–2281CrossRefGoogle Scholar
  23. 23.
    Zareiee M, Orouji AA, Mehrad M (2016) A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region. J Comput Electron 15(2):611–618CrossRefGoogle Scholar
  24. 24.
    Anvarifard MK (2016) Successfully controlled potential distribution in a novel high-voltage and high-frequency SOI MESFET. IEEE Trans Device Mater Reliab 16:631–637CrossRefGoogle Scholar
  25. 25.
    Mohtaram M, Orouji AA, Ramezani Z (2018) A novel SOI MESFET to improve the equipotential contour distributions by using an oxide barrier. Silicon, pp 1–11Google Scholar
  26. 26.
    Jia H, Pei X, Zh S, Zh H (2015) Improved performance of 4H-silicon carbide metal semiconductor field effect transistors with multi-recessed source/drain drift regions. Mater Sci Semicond Process 31:240–244CrossRefGoogle Scholar
  27. 27.
    Sharma YK, Ahyi AC, Smith I, Modic A, Xu Y, Garfunkel EL, Dhar S, Feldman LC, Williams JR (2013) High-mobility stable 4H-SIC MOSFETs using a thin PSG interfacial passivation layer. IEEE Electron Device Letters 34:175–177CrossRefGoogle Scholar
  28. 28.
    Mehrad M, Zareiee M, Orouji AA (2017) Controlled kink effect in a novel high-voltage LDMOS transistor by creating local minimum in energy band diagram. IEEE T Electron Dev 64(10):4213–4218Google Scholar
  29. 29.
    Goel AK, Tan TH (2006) High-temperature and self-heating effects in fully depleted SOI MOSFETs. Microchem J 37:963–975Google Scholar
  30. 30.
    Zareiee M (2019) A new structure for lateral double diffused MOSFET to control the breakdown voltage and the on-resistance. Silicon:1–9Google Scholar
  31. 31.
    Zareiee M (2019) A novel dual trench gate power device by ffective drift region structure. Superlattices and Icrostructures 125:8–15CrossRefGoogle Scholar
  32. 32.
    Mehrad M (2016) Omega shape channel LDMOS: a novel structure for high voltage applications. Physica E: Low-dimensional Systems and Nanostructures. Physica E 75:196–201Google Scholar
  33. 33.
    Kumar A, Gupta N, Chaujar R (2016) Power gain assessment of ITO based transparent gate Recessed Channel (TGRC) MOSFET for RF/wireless applications. Superlattice Microst 91:290–301Google Scholar
  34. 34.
    Naderi A, Heirani F (2018) A novel SOI-MESFET with symmetrical oxide boxes at both sides of gate and extended drift region into the buried oxide. AEU Int J Electron Commun 85:91–98CrossRefGoogle Scholar
  35. 35.
    Tahne BA, Naderi A (2017) SLD-MOSCNT: a new MOSCNT with step-linear doping profile in the source and drain regions. International Journal of Modern Physics B 31:1650242CrossRefGoogle Scholar
  36. 36.
    Naderi A, Satari KM, Heirani F (2018) SOI-MESFET with a layer of metal in buried oxide and a layer of SiO2 in channel to improve RF and breakdown characteristics. Mat Sci Semicon Proc 88:57–64Google Scholar
  37. 37.
    Naderi A, Heirani F (2017) Improvement in the performance of SOI-MESFETs by T-shaped oxide part at channel region: DC and RF characteristics. Superlattice Microst 111:1022–1033CrossRefGoogle Scholar

Copyright information

© Springer Nature B.V. 2019

Authors and Affiliations

  1. 1.Advanced Skills CenterUniversity of Applied Science and TechnologyKermanshahIran
  2. 2.Electrical Engineering Department, Energy FacultyKermanshah University of TechnologyKermanshahIran

Personalised recommendations